Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 401

• Channel Interrupt Status Register (MLB_CICR). Reflects the
channel interrupt status of the individual logical channels. These
bits are set by hardware when a channel interrupt is generated. The
channel interrupt bits are sticky and can only be reset by software.
• Channel Status Configuration Registers (MLB_CSCRx). Reflects
the status of the current buffer and previous buffer for a given logi-
cal channel. The definition of the bit fields in this register vary
dependant on the selected channel type.
• Channel Current Buffer Configuration Registers
(MLB_CCBCRx), Channel Next Buffer Configuration Registers
(MLB_CNBCRx), Local Buffer Configuration Registers
(MLB_LCBCRx). These registers allow programs to control and
monitor the buffers used in the MLB network.
Clocking
Media Local Bus Clock. This clock is generated by the MLB controller
that is synchronized to the MOST network and provides the timing for
the entire MLB interface at 49.152 MHz at Fs=48 kHz.
Functional Description
Once per MOST network frame, the MLB controller generates a unique
frame sync pattern on the
defines the byte boundary and the channel boundary for the
lines of all MLB devices.
MLBDAT
The MLB controller manages the arbitration for all the channels on the
MLB and grants bandwidth for all the MLB devices. A MLB physical
channel is defined as four bytes wide, or a quadlet. Physical channels can
be grouped into multiple qualdets (which do not have to be consecutive)
ADSP-214xx SHARC Processor Hardware Reference
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line. The end of the frame sync pattern
MLBSIG
Media Local Bus
and
MLBSIG
8-5