Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 802

Processor Booting
8-Bit SPI Packing
Figure 23-8 shows how an 8-bit SPI host packs 48-bit instructions exe-
cuted at PM addresses PMaddr0 and PMaddr1. For 8-bit hosts, four 8-bit
words pack into the shift register to generate a 32-bit word. The 32-bit
word shifts to internal program memory during the load of the
256-instruction word kernel.
The following code shows a 48-bit instruction executed:
[PMaddr0] 0x112233445566
[PMaddr1] 0x7788AABBCCDD
Figure 23-8. 8-Bit SPI Slave Packing
The 8-bit SPI host packs or prearranges the data as:
SPI word 1 = 0x66
SPI word 2 = 0x55
SPI word 3 = 0x44
SPI word 4 = 0x33
SPI word 5 = 0x22
SPI word 6= 0x11
The initial boot of the 256-word loader kernel requires an 8-bit host to
transmit 1536 x 8-bit words. The SPI DMA count value of 0x180 is equal
23-20
www.BDTIC.com/ADI
32
32
DMA
SPI_MOSI_I/SPI_MISO_I
SPI word 7 = 0xDD
SPI word 8 = 0xCC
SPI word 9 = 0xBB
SPI word 10 = 0xAA
SPI word 11 = 0x88
SPI word 12= 0x77
ADSP-214xx SHARC Processor Hardware Reference
32
Internal
Memory