Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 379

PWMPERIOD

1
T -----------------------------------------
=

AH
2
PWMTM 1
+
2
count
pwm_ah
pwm_al
PWM PHASE BIT
PWM INTERRUPT
LATCH BIT
Figure 7-3. Center-Aligned Paired PWM in Double Update Mode,
Low Polarity
where subscript 1 refers to the value of that register during the first half
cycle and subscript 2 refers to the value during the second half cycle. The
corresponding duty cycles are:
T
AL
---------- -
d AL
= =
T S
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
PWMPERIOD
2
----------------------------------------- PWMCHA
+ +
2
PWMTM 1
0
PWMCHA 1
2xPWMDT 1
PWMTM 1
(
PWMCHA PWMCHA
+
1 1
-- - ------------------------------------------------------------------------------------------------------------------------------------------ -
–
(
2 PWMPERIOD 1
Pulse Width Modulation
PWMCHA PWMDT
+ –
1 2
2
PWMTM 2
0
2
PWMCHA 2
2xPWMDT 2
PWMDT
+
2 1
PWMPERIOD 2
+

× t
PWMDT
–

PCLK
1 2
PWMTM 2
+
2
PWMTM 2
)
PWMDT
+
2
)
7-11