Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 676

Effect Latency
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
Peripheral Timers Effect Latency
After the timer registers are configured the effect latency is 3
enable and 2
PCLK
bit is set.
TIMEN
When the timer is enabled, the count register is loaded according to the
operation mode specified in the
abled, the counter registers retain their state; when the timer is re-enabled,
the counter is reinitialized based on the operating mode
The program should never write the counter value directly.
TIMER ENABLE
CCLK
PCL K
PWMOUT
TIMER DISABLE
CCL K
Figure 16-9. Timer PWM Enable and Disable Timing
16-20
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cycles disable. The timer starts 3
TMxCTL
SET
TIM EN
TCOUNT TCOUNT TCOUNT
= XX = XX =XX
SET TIMER
TIM DIS DISABLED
TCOUNT T COUNT TCOUNT
= M =M +1 =M +1
ADSP-214xx SHARC Processor Hardware Reference
PCLK
register. When the timer is dis-
(Figure
TIMER
ENABL ED
TCOUNT TCOUNT TCOUNT
=1 =2 = 3
T COUNT T COUNT
=M+ 1 =M+ 1
cycles
PCLK
cycles after the
16-9).
T COUNT
= 4
TMxPRD = 0X2
TMxW = 0X1