Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 860

ADSP-2146x External Port Registers
Table A-14. DDR2CTL3 Register Bit Descriptions (RW) (Cont'd)
Bit
5–3
6, 2
9–7
10
11
12
13
15–14
A-34
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Name Description
DDR2AL Additive Latency. Additive latency reduces command bus
conflicts to enable commands to be issued more effi-
ciently. Note thate the DDR2 controller performance is
primary regardless of the AL settings.
000 = 0 clock cycles.
001 = 1 clock cycles.
...
101 = 5 clock cycles.
110, 111 = Reserved.
The basic rule for additive latency is defined as:
AL <= t
AL = 3–0.
If AL = 4, tRCD is increased by 1 cycle, increasing overall
latency.
DDR2ODT On Die Termination Value.
00 = ODT disabled
01 = 75 ohm
10 = 150 ohm
11 = 50 ohm
Reserved
DDR2DQSDIS Differential DQS Disable.
0 = Enable
1 = Disable
Reserved
DDR2OBDIS Output Buffer Disable.
0 = Enable
1 = Disable
Reserved
DDR2EXTMR1 Extended Mode Register 1.
Must be set to 01.
ADSP-214xx SHARC Processor Hardware Reference
. Example: t
RCDmin–1 RCD
and
DQS DQS
DQS
is 4 cycles then