Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 912

Peripheral Registers
Table A-50. FIRDMASTAT Register Bit Descriptions (RO)
Bits Name
11–7 CURCHNL
13–12 CURITER
31–14 Reserved
FIR Debug Registers (FIRDEBUGCTL, FIRDBGADDR)
This register, shown in
the debug operation of the FIR accelerator and should only be used in
debug mode.
31 30
15
FIR_ADRINC
Address Auto Increment
FIR_DBGMEM
Local Memory Access
Figure A-39. FIRDEBUGCTL Register
A-86
www.BDTIC.com/ADI
Description
Current Channel. Channel that is being processed in the
TDM slot. Zero indicates the last slot.
Current MAC Iteration. Current MAC iteration in multi
iteration mode. Zero indicates the final iteration.
Figure A-39
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
ADSP-214xx SHARC Processor Hardware Reference
and described in Table
21 20 19 18 17 16
6 5 4 3 2 1 0
FIR_DBGMODE
Debug Mode Enable
FIR_HLD
Hold or Single Step
FIR_RUN
Release MAC
A-51, control