Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 548

Programming Model
5. Set the desired values for the N_SET variable using the
bits in the
6. Set the
IDP_FIFO_GTN_INT
to HIGH and set the corresponding bit in the
ter to LOW to unmask the interrupt. Set bit 8 of the
DAI_IMASK_PRI
high priority or low priority core interrupt when the number of
words in the FIFO is greater than the value of N set.
7. Enable the PDAP by setting
register), if required.
8. Enable the IDP by setting the
register) and the

In older SHARC processors, the IDP starts shifting data before the
IDP is enabled. However, the shifted data is latched at the next
frame sync edge only if the IDP is enabled. Therefore, whether the
first channel received by the IDP is left/right depends on the
instant when the IDP is enabled— which may lead to channel
swapping.
Additional Notes
When IDPs are used to receive data from external devices, there is a
sequence to be followed to enable the IDP ports when configured to
receive data in I
channel shift or swap.
1. Connect the frame sync internally using the SRU (Signal Routing
Unit) to the DAI interrupt.
2. Configure the DAI interrupt (MISCA) for the inactive edge of the
frame sync.
11-28
www.BDTIC.com/ADI
register.
IDP_CTL0
bit (bit 8 of the
register (
IDP_FIFO_GTN_INT
bits in the
IDP_ENx
2
S mode. Failing to follow this sequence can give rise to
ADSP-214xx SHARC Processor Hardware Reference
DAI_IMASK_RE
DAI_IMASK_FE
) as needed to generate a
(bit 31 in the
IDP_PDAP_EN
bit (bit 7 in the
IDP_EN
register.
IDP_CTL1
IDP_NSET
register)
regis-
IDP_PP_CTL
IDP_CTL0