Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 605

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Timing Example for I2S Mode

S mode, the frame sync should be driven at the falling edge of

In other words, the frame sync edge should coincide with the falling edge

. To satisfy this requirement, the phase of the frame sync

should be programmed accordingly in the

For example, assume that the input clock source for both clock and frame

sync are the same and both the clock and frame sync are enabled at the

same time. Also assume that the clock divisor value needed to generate the

sync divisor value should be

By default, for phase = 0, the rising edge of both

coincide. To make sure that the frame sync edges coincides with the fall-

ing edge of the

/2 = 2. It can be done by following instructions:

ustat1=CLKDIV|((CLKDIV/2) << 20);

dm(PCG_CTLx1) = ustat1;

For details on how to program phase of the frame sync see

Model" on page

Operating Modes

The following sections provide information on the operating modes of the

precision clock generator.

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

= 4. Then, for a 32-bit word length, the frame

, the phase value needs to be programmed as

Precision Clock Generator

and frame sync will

"Programming

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