Slave Mode; Functional Description - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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The frame sync is continuously active when

should not be less than the serial word length minus one (the value of the

field in the serial port control register), as this may cause an external

device to abort the current operation or cause other unpredictable results.

If the serial port is not being used, the

ter for dividing an external clock or for generating a periodic pulse or

periodic interrupt. The serial port must be enabled for this mode of oper-

ation to work properly.

Programs should not use master clock/frame sync on SPORTs to

drive ADCs/DACs in high fidelity audio systems. Use the precision

clock generator (PCG) instead.

Slave Mode

Exercise caution when operating with externally-generated transmit clocks

near the frequency of

delay between when the clock arrives at the

data is output. This delay may limit the receiver's speed of operation.

Refer to the appropriate product data sheet for exact timing specifications.

Externally-generated late transmit frame syncs also experience a delay

from when they arrive to when data is output. This can also limit the max-

imum serial clock speed. Refer to the appropriate product data sheet for

exact timing specifications.

Functional Description

The following sections provides general information on the function of

"Architecture"

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/4 of the processor's internal clock. There is a

ADSP-214xx SHARC Processor Hardware Reference

= 0. The value of

divisor can be used as a coun-

node and when

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