Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 928

Peripheral Registers
Channel Control Registers (MLB_CECRx)
These registers define the basic attributes of a given logical channel, such
as the channel enable, channel direction, and channel address. The defini-
tion of the bit fields in these registers vary by the selected channel type.
Figure A-48 and
and control channels and
tion for for synchronous channels.
31 30
CE
Channel x Enable
CTRAN
Channel x Transmit Select
CTYPE (29–28)
Channel x Type Select
15 14
PCTH (12–8)
Packet Count Threshold,
I/O Mode
Figure A-48. MLB_CECRx Register (Asynch and Control Channels)
A-102
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Table A-66 provide information for for asynchronous
Figure A-49
29 28 27 26 25 24 23 22
13 12 11 10 9 8 7 6
ADSP-214xx SHARC Processor Hardware Reference
and Table A-67 provide informa-
21 20 19 18 17 16
MASK (23–16)
Channel x Interrupt Mask
MDS (26–25)
Channel x Mode Select
PCE
Packet Count Enable
5 4 3 2 1 0
CA (7–0)
Channel Address