Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 340

FIR Accelerator

The
FIRCTL2
ming individual FIR channels with different control attributes.
Buffer Length
Register
Figure 6-7. Circular Buffer Addressing
Interrupts
The FIR accelerator has two interrupts
through the programmable interrupt priority control register
(see Appendix B, Peripheral Interrupt
are used to connect FIR interrupts to the peripheral interrupt inputs
ACC1I
of the core.
Table 6-3. Overview of FIR Interrupts
Interrupt Source
FIR (2 channels)
One interrupt line is shared by all the DMA interrupts and the other by
MAC status interrupts. Separate status registers are provided to further
differentiate the various sources.
6-44
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register is part of the FIR TCB. This allows program-
20
19
.
.
.
5
4
3
2
1
Interrupt Condition Interrupt
Completion
- Window Complete - internal trans-
- Channel Complete fer completion
- MAC status
ADSP-214xx SHARC Processor Hardware Reference
Index Register
Base Register
(Table 6-3) that are programmable
Control). Source bits
Interrupt
Acknowledge
RTI instruction Need to route
and
ACC0I
Default IVT
ACCx1 (PICRx)
to any PxxI