Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 768

Phase-Locked Loop (PLL)
PLL Multiplier
The PLL multiplier is controlled by hardware or software and based on
the PLL multiplier settings below.
• Hardware—through the clock configuration pins (
• Software—the hardware settings are overridden through the
bits
PLLM Hardware Control
On power-up, the
which cannot be changed during runtime. After booting however, numer-
ous other ratios (slowing or speeding up the clock) can be selected through
software control.
For information on the internal clock to
by the various processors, see the product specific data sheet.
PLLM Software Control
Programs control the PLL through the
( ) bits can be configured to set a multiplier range of 0 to 63. This
PLLM
allows the PLL to be programmed dynamically in software to achieve a
higher or slower core instruction rate depending on a particular system's
requirements.
The reset value of the
ply ratio settings. This value can be reprogrammed in the boot kernel to
take effect immediately after start- up.
22-4
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pins are used to select core to
CLK_CFG1–0
bits is derived from the
PLLM
ADSP-214xx SHARC Processor Hardware Reference
CLK_CFG1–0
frequency ratios supported
CLKIN
register. The PLL multiplier
PMCTL
CLK_CFG1–0
)
PLLM
ratios
CLKIN
pin multi-