Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual

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ADSP-2136x SHARC

Processor

Hardware Reference

Includes ADSP-21362, ADSP-21363,

ADSP-21364, ADSP-21365, ADSP-21366

Revision 2.0, June 2009

Part Number

82-000501-01

Analog Devices, Inc.

One Technology Way

Norwood, Mass. 02062-9106

www.BDTIC.com/ADI

Table of Contents

Summary of Contents for Analog Devices SHARC ADSP-2136 Series

Page 1 ADSP-2136x SHARC Processor ® Hardware Reference Includes ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 Revision 2.0, June 2009 Part Number 82-000501-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 www.BDTIC.com/ADI...
Page 2 Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use;...
Page 3: Table Of Contents
CONTENTS PREFACE Purpose of This Manual ............... xxxi Intended Audience ............... xxxi Manual Contents ................ xxxii What’s New in This Manual ............xxxiv Technical or Customer Support ..........xxxvi Supported Processors ..............xxxvii Product Information ..............xxxvii MyAnalog.com ..............xxxviii Processor Product Information ..........
Page 4 Contents INTRODUCTION ADSP-2136x SHARC Design Advantages ........1-1 SHARC Family Product Offerings ........... 1-5 Processor Architectural Overview ..........1-6 Processor Core ................ 1-7 Processor Peripherals ............... 1-7 I/O Processor ..............1-7 Digital Applications Interface (DAI) ........1-9 Development Tools ..............1-10 Architecture Enhancements ............
Page 5 Contents DMA Channel Allocation ............. 2-10 DMA Channel Priority ............... 2-11 DMA Channel Arbitration Modes ......... 2-14 Peripheral DMA Bus ............2-14 Rotating Priority by Group ............ 2-15 DMA Channel Interrupts ............2-16 Internal Transfer Completion ..........2-16 DMA Channel Interrupt Priorities ......... 2-16 Interrupt Versus Channel Priorities ........
Page 6 Contents TCB Storage ................2-30 Serial Port TCB ..............2-30 Parallel Port TCB ..............2-30 SPI TCB ................2-31 I/O Processor Register Access ............2-32 IOP Access Conditions ............2-32 Interrupt Latency ............. 2-33 TCB Chain Loading Access ........... 2-34 IOP Register Access Arbitration ..........
Page 7 Contents Functional Description ............4-4 Multiplexed Operation ............4-4 Address Cycles ..............4-4 Data Cycles ................. 4-5 Data Buffers ................4-6 Read Path ................4-6 Write Path ................4-7 Operation Modes ..............4-8 8-Bit Mode ................. 4-8 16-Bit Mode ............... 4-9 Parallel Port Registers ..............
Page 8 Contents Core-Stall Driven Transfers ..........4-17 Interrupts ................... 4-18 DMA Interrupts ..............4-19 Core Interrupts ..............4-19 Throughput ................4-19 8-Bit Access ................4-20 16-Bit Access ................ 4-21 8-Bit Versus 16-Bit SRAM Modes ......... 4-22 Parallel Port Effect Latency ............ 4-23 Programming Model ..............
Page 9 Contents Miscellaneous Buffers ............5-12 Signal Routing Matrix by Groups ........... 5-13 DAI Group Routing .............. 5-14 Rules for SRU Connections ........... 5-16 Making SRU Connections ............. 5-16 Routing Capabilities .............. 5-20 Default Routing ................5-21 Interrupt Controller ..............5-24 System versus Exception Interrupts ........
Page 10 Contents SRU SPORT Receive Master ........... 6-7 SRU SPORT Signal Integrity ..........6-7 Functional Description ..............6-9 Registers ..................6-10 Control Registers (SPCTLx) ..........6-12 Multichannel Control Registers (SPMCTLxy) ....... 6-12 Data Buffers ................. 6-13 Transmit Buffers (TXSPxA/B) ........... 6-13 Transmit Path ...............
Page 11 Contents Master Clock ..............6-25 Master Frame Sync ............6-26 Slave Mode ............... 6-26 Clock Source (ICLK, MSTR) ..........6-27 Sampling Edge (CKRE) ............6-27 Frame Sync Options ..............6-28 Framed Versus Unframed Frame Syncs ........6-28 Internal Versus External Frame Syncs (IFS, IMFS, MSTR) ............
Page 12 Contents Selecting Transmit and Receive Channel Order (L_FIRST) ..............6-39 Multichannel Operation ............6-40 Frame Syncs Signals ............6-42 Transmit Valid Signals ............6-43 Multichannel Mode Control Bits ........6-44 Number of Channels (NCH) ..........6-45 Frame Delay (MFD) ............6-45 Channel Selection Registers ...........
Page 13 Contents Buffer Hang Disable (BHD) ..........6-55 Effect Latency ............... 6-55 Programming Model ..............6-56 Setting Up and Starting Chained DMA ........6-56 Enter DMA Chain Insertion Mode ........6-57 Programming Examples ............... 6-57 SERIAL PERIPHERAL INTERFACE PORTS Features ..................7-1 Pin Descriptions ................
Page 14 Contents Status Register (SPISTATx) ........... 7-18 Multi Master Error (MME) ..........7-19 Transmission Error Bit (TUNF) ........7-20 Reception Error Bit (ROVF) ..........7-20 Transmit Collision Error Bit (TXCOL) ......7-20 BAUD Rate Register (SPIBAUDx) ........7-21 DMA Control Register (SPIDMACx) ........7-21 Data Transfer Types ..............
Page 15 Contents Loopback Routing ............7-33 Programming Model ..............7-33 Master Mode Core Transfers ..........7-33 Slave Mode Core Transfers ............. 7-35 Master Mode DMA Transfers ..........7-36 Slave Mode DMA Transfers ........... 7-38 Chained DMA Transfers ............7-39 Stopping Core Transfers ............7-40 Stopping DMA Transfers ............
Page 16 Contents Pin Descriptions ..............8-11 SRU Programming ............8-12 Register Descriptions ............8-12 Control Register (IDP_PP_CTL) ........8-12 PDAP Data Packing .............. 8-13 Mode 11 (No Packing) ............. 8-13 Mode 10 (Packing by 2) ............ 8-14 Mode 01 (Packing by 3) ............ 8-14 Mode 00 (Packing by 4) ............
Page 17 Contents Servicing Interrupts ............8-24 Debug Features ................8-24 Buffer Hang Disable .............. 8-25 Shadow Registers ..............8-25 Core FIFO Write ..............8-25 IDP Effect Latency ..............8-26 Programming Model ..............8-26 Setting Miscellaneous Bits ............. 8-26 Starting Core Interrupt-Driven Transfer ......... 8-27 Starting A Standard DMA Transfer ........
Page 18 Contents Operation ..................9-7 Mode Selection ............... 9-8 Pulse Width Modulation Mode (PWM_OUT) ....9-9 PWM Waveform Generation ......... 9-12 Single-Pulse Generation ..........9-13 Pulse Mode ..............9-13 Pulse Width Count and Capture Mode (WDTH_CAP) ..9-14 External Event Watchdog Mode (EXT_CLK) ....9-17 Interrupts ...................
Page 19 Contents Operation Modes ................ 10-6 Groups Synchronization ............10-6 PWM Timer ..............10-7 Edge-Aligned Mode ............10-8 Center-Aligned Mode ............10-9 Switching Frequencies ............10-11 Dead Time ................10-12 Duty Cycles ................ 10-13 Duty Cycles and Dead Time ..........10-13 Over-Modulation ............
Page 20 Contents Pin Descriptions ..............11-3 SRU Programming ..............11-4 Functional Description ............11-5 Input Data Format ..............11-7 Output Data Mode ............... 11-8 Operation Modes ..............11-9 Standalone Mode .............. 11-9 Full Serial Mode ............... 11-9 Register Descriptions ............11-9 Control Register (DITCTL) ..........
Page 21 Contents Emphasized Audio Data ..........11-19 Single-Channel Double-Frequency Mode ......11-19 Interrupts ................. 11-20 Transmitter Interrupt ............11-20 Receiver Interrupts .............. 11-20 Debug Features ................. 11-21 Loopback Routing ............... 11-21 Programming Model ..............11-21 Programming the Transmitter ..........11-21 Programming the Receiver ........... 11-22 Interrupted Data Streams on the Receiver ......
Page 22 Contents Control Registers (SRCCTLn) ..........12-11 Data Format ..............12-12 Word Width ..............12-12 Ratio Registesr (SRCRATx) ..........12-13 Operation Modes ..............12-13 TDM Daisy Chain Mode ............ 12-14 TDM Output Daisy Chain ..........12-14 TDM Input Daisy Chain ..........12-15 Bypass Mode ...............
Page 23 Contents External Trigger Mode ..............13-9 Frame Sync ................. 13-10 Phase Shift ................13-11 Phase Shift Settings ............. 13-11 Pulse Width ................ 13-13 Bypass Mode ............... 13-13 Bypass as a Pass Through ..........13-14 Bypass as a One-Shot ............13-14 Programming Examples .............
Page 24 Contents Output Clock Generator ............14-9 Core Clock (CCLK) ............14-9 Peripheral Clock (PCLK) ..........14-10 Bypass Clock ..............14-10 Power Savings ..............14-10 Power Supplies ................. 14-11 Power Supply for the PLL ............ 14-11 Power-Up Sequence ..............14-11 Input Clock ................ 14-11 PLL Start-Up ..............
Page 25 Contents System Components ..............14-26 Supervisory Circuits ............14-26 Designing for High Frequency Operation ........14-28 Other Recommendations and Suggestions ......14-29 Decoupling and Grounding ..........14-29 Oscilloscope Probes ............. 14-30 Recommended Reading ............14-31 Processor Booting ..............14-32 Boot Mechanisms ..............14-32 Booting Process ..............
Page 26 Contents 8-Bit SPI Packing ............14-46 Kernel Boot Time ............... 14-47 Definition of Terms ............14-48 REGISTERS REFERENCE I/O Processor Registers ..............A-2 Notes on Reading Register Drawings ........A-3 System Control Register (SYSCTL) ......... A-4 Power Management Control Register (PMCTL) ..............A-6 Peripheral Registers ..............
Page 27 Contents PWM Global Status Register (PWMGSTAT) ....A-24 PWM Control Register (PWMCTLx) ....... A-25 PWM Status Registers (PWMSTATx) ....... A-26 PWM Period Registers (PWMPERIODx) ......A-27 PWM Output Disable Registers (PWMSEGx) ....A-27 PWM Polarity Select Registers (PWMPOLx) ....A-28 PWM Channel Duty Control Registers (PWMAx, PWMBx) ............
Page 28 Contents Parallel Data Acquisition Port Control Register (IDP_PP_CTL) ............. A-50 Input Data Port FIFO Register (IDP_FIFO) ..... A-53 IDP Status Register (DAI_STAT0) ........A-54 IDP Status Register 1 (DAI_STAT1) ......... A-56 Peripheral Timer Registers ............. A-56 Timer Configuration Registers (TMxCTL) ......A-56 Timer Status Registers (TMxSTAT) ........
Page 29 Contents Receive Status Register (DIRSTAT) ......A-75 Receive Status Registers for Subframe A (DIRCHANL) ............A-77 Receive Status Registers for Subframe B (DIRCHANR) ............A-77 DAI Interrupt Controller Registers ........A-77 DAI Status Register .............. A-78 Digital Applications Interface Status Register (DAI_STAT) ..............
Page 30 Contents INTERRUPTS Programmable Interrupt Control Registers ........B-1 Programmable Interrupt Control Register 0 (PICR0) ....B-3 Programmable Interrupt Control Register 1 (PICR1) ....B-4 Programmable Interrupt Control Register 2 (PICR2) ....B-5 Programmable Interrupt Control Register 3 (PICR3) ....B-5 AUDIO FRAME FORMATS Overview ..................
Page 31: Preface
ADSP-21362/3/4/5/6 Processors contains information about the peripheral set and I/O properties for these products. These are 32-bit, fixed- and floating-point digital signal processors from Analog Devices for use in computing, communications, and consumer applications. The manual provides information on the processor’s I/O architecture and the operation of the peripherals associated with each model.
Page 32: Manual Contents
Manual Contents Manual Contents This manual provides detailed information about the ADSP-2136x pro- cessors in the following chapters: • Chapter 1, “Introduction” Provides an architectural overview of the ADSP-2136x SHARC processors. • Chapter 2, “I/O Processor” Describes input/output processor architecture, and provides direct memory access (DMA) procedures for the processor peripherals.
Page 33 Preface • Chapter 8, “Input Data Port” Discusses the function of the input data port (IDP) which provides a low overhead method of routing signal routing unit (SRU) sig- nals back to the core’s memory. • Chapter 9, “Peripheral Timers” The processor processors contain three identical 32-bit timers that can be used to interface with external devices.
Page 34: What's New In This Manual
What’s New in This Manual • Appendix A, “Registers Reference” Provides a graphical presentation of all registers and describes the bit usage in each register. • Appendix B “Interrupts” Provides information on the programmable interrupt control regis- ters ( ). These registers allow programs to substitute the PICRx default interrupts for some other interrupt source.
Page 35 Preface Where appropriate, the chapters contain the following informa- tion, presented in this order: • Primary features • Hardware interface (pins) • Basic function of the peripheral • Primary registers used by this peripheral • Basic peripheral operation, including DMA •...
Page 36: Technical Or Customer Support
), Mode Mask register ( LIRPTL MMASK Technical or Customer Support You can reach Analog Devices, Inc. Customer Support in the following ways: • Visit the Embedded Processing and DSP products Web site at http://www.analog.com/processors/technicalSupport • E-mail tools questions to processor.tools.support@analog.com...
Page 37: Supported Processors
Preface Supported Processors The following is the list of Analog Devices, Inc. processors supported in VisualDSP++®. TigerSHARC® (ADSP-TSxxx) Processors The name TigerSHARC refers to a family of floa ting-point and fixed-point [8-bit, 16-bit, and 32-bit] processors. VisualDSP++ currently supports the following TigerSHARC families: ADSP-TS101 and ADSP-TS20x.
Page 38: Myanalog.com
Product Information MyAnalog.com is a free feature of the Analog Devices Web site that allows MyAnalog.com customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests.
Page 39: Related Documents
Preface • Fax questions or requests for information to 1-781-461-3010 (North America) +49-89-76903-157 (Europe) • Access the FTP Web site at ftp ftp.analog.com ftp 137.71.25.69) ftp://ftp.analog.com Related Documents The following publications that describe the ADSP-2136x processor (and related processors) are available online: •...
Page 40: Online Technical Documentation
Product Information Online Technical Documentation Online documentation comprises the VisualDSP++ Help system, software tools manuals, hardware tools manuals, processor manuals, the Dinkum Abridged C++ library, and Flexible License Manager (FlexLM) network license manager software documentation. You can easily search across the entire VisualDSP++ documentation set for any topic of interest.
Page 41: Accessing Documentation From Windows
• Double-click any file that is part of the VisualDSP++ documenta- tion set. Using the Windows Start Button • Access VisualDSP++ online Help by clicking the Start button and choosing Programs, Analog Devices, VisualDSP++, and VisualDSP++ Documentation. files by clicking the Start button and choosing • Access the .PDF...
Page 42: Conventions
Conventions Conventions Text conventions used in this manual are identified and described as follows. Example Description Close command Titles in reference sections indicate the location of an item within the Visu- (File menu) alDSP++ environment’s menu system (for example, the Close command appears on the File menu).
Page 43 Preface  Additional conventions, which apply only to specific chapters, may appear throughout this document. ADSP-2136x SHARC Processor Hardware Reference xliii www.BDTIC.com/ADI...
Page 44 Conventions xliv ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 45: Adsp-2136X Sharc Design Advantages
1 INTRODUCTION The ADSP-2136x SHARC processors are high performance 32-bit proces- sors used for high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. By adding on-chip SRAM, integrated I/O peripherals, and an additional processing element for single-instruc- tion, multiple-data (SIMD) support, this processor builds on the ADSP-21000 family DSP core to form a complete system-on-a-chip.
Page 46 ADSP-2136x SHARC Design Advantages a single cycle. The buses and instruction cache provide rapid, unimpeded data flow to the core, thereby maintaining the execution rate. The ADSP-2136x processors contain the following architectural features: • Two processing elements (PEx and PEy), each containing 32-bit IEEE floating-point computation units—multiplier, arithmetic logic unit (ALU), shifter, and data register file.
Page 47 Introduction Figure 1-1 illustrates a typical single processor system. ADSP-2136 x RE SETOUT CLKIN CLOCK X TAL LATCH AD1 5-0 ADDR CLK_CFG1-0 PARALLEL PORT BOOTCFG1 -0 DATA RAM, ROM FLAG3-1 BOO T ROM I /O DEVI CE FLAG0 (OPTI ONAL) DAI_P1 DAI_ P2 S DAT...
Page 48 ADSP-2136x SHARC Design Advantages register file, supply two operands to the ALU, supply two operands to the multiplier, and receive three results from the ALU and mul- tiplier. The processor’s 48-bit orthogonal instruction word supports parallel data transfers and arithmetic operations in the same instruction.
Page 49: Sharc Family Product Offerings
Introduction • Input data port (IDP). The IDP provides an additional input path to the processor core, configurable as eight channels of serial data or seven channels of serial data and a single channel of up to 20-bit wide parallel data. •...
Page 50: Processor Architectural Overview
333 MHz 1 The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Pro- tection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. 2 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES, MPEG2 AAC, MP3, and functions like Bass management, Delay, Speaker equalization, Graphic equalization, and more.
Page 51: Processor Core
Introduction Processor Core The processor core of the processor consists of two processing elements (each with three computation units and data register file), a program sequencer, two data address generators, a timer, and an instruction cache. All digital signal processing occurs in the processor core. For complete information, see the SHARC Processor Programming Reference.
Page 52 Processor Architectural Overview associated with it to service the dual serial data pins. Programmable data direction provides greater flexibility for serial communications. Serial port data can automatically transfer to and from on-chip memory using DMA. Each of the serial ports offers a TDM multichannel mode (up to 128 channels) and supports μ-law or A-law companding.
Page 53: Digital Applications Interface (Dai)
Introduction ROM-based security. For those processors with application code in the on-chip ROM, an optional ROM securityfeature is included. This feature provides hardware support for securing user software code by preventing unauthorized reading from the enabled code. The processor does not boot-load any external code, executing exclusively from internal ROM.
Page 54: Development Tools
Development Tools Development Tools The ADSP-2136x processor is supported by VisualDSP++, an easy to use Integrated Development and Debugging Environment (IDDE). VisualDSP++ allows you to manage projects from start to finish from within a single, integrated interface. Because the project development and debug environments are integrated, you can move easily between editing, building, and debugging activities.
Page 55: I/O Architecture Enhancements
Introduction I/O Architecture Enhancements The I/O processor provides greater throughput than the ADSP-2106x processors. The DMA controller supports 25 channels compared to 14 channels on the ADSP-2116x processor. Instruction Set Enhancements The ADSP-2136x processor provides source code compatibility with the previous SHARC processor family members, to the assembly source code level.
Page 56 Architecture Enhancements 1-12 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 57 2 I/O PROCESSOR In applications that use extensive off-chip data I/O, programs may find it beneficial to use a processor resource other than the processor core to per- form data transfers. The ADSP-2136x pro cessor contains an I/O processor (IOP) that supports a variety of DMA (direct memory access) operations. Each DMA operation transfers an entire block of data.
Page 58: Dma Controller Operation
DMA Controller Operation  The I/O processor runs at CCLK ÷ 2 clock speed. • Internal memory ↔ SPORT (DAI) • Internal memory ← IDP (DAI) unidirectional • Internal memory ↔ SPI • Internal memory ↔ Internal memory (MTM) By managing DMA, the I/O processor frees the processor core, allowing it to perform other operations while off-chip data I/O occurs as a back- ground task.
Page 59: Dma Transfers Between Internal Memory
I/O Processor An instance where standard DMA can be used is to copy data from a peripheral to internal memory for processor booting. With the help of the loader tool, the tag (header information) of the boot stream is decoded to get the storage information which includes the index, modify, and count of a specific array to start another standard DMA.
Page 60: General Procedure For Configuring Dma
General Procedure for Configuring DMA General Procedure for Configuring DMA To configure the processors to use DMA, use the following general procedure. 1. Configure the peripheral(s): • Parallel port (PPCTL) • Serial ports (SPORTs) • Serial peripheral interface ports (SPI) •...
Page 61: Summary
I/O Processor 6. Start the DMA • Set the applicable bits in the appropriate registers. The following sections provide more detailed DMA information for spe- cific peripherals. Summary Because the IOP registers are memory-mapped, the processors have access to program DMA operations. A program sets up a DMA channel by writ- ing the transfer's parameters to the DMA parameter registers.
Page 62: Standard Dma Parameter Registers
IOP Registers Standard DMA Parameter Registers The parameter registers described below control the source and destina- tion of the data, the size of the data buffer, and the step size used. Index registers. Shown in Table 2-2, provide an internal memory address, acting as a pointer to the next internal memory DMA read or write loca- tion.
Page 63 I/O Processor Table 2-3. Modify Registers Register Name Width (Bits) Description IMSP0–5A SPORTA IMSP0–5B SPORTB IMSPI IMSPIB SPIB IDP_DMA_M0–7 IDP_DMA_M0–7A IDP modify A (ping pong) IDP_DMA_M0–7B IDP modify B (ping pong) IMMTMW MTM Write IMMTMR MTM Read IMPP Parallel Port EMPP Parallel Port (external address) Count registers.
Page 64: Standard Dma Status Registers
IOP Registers Chain pointer registers. Shown in Table 2-5, hold the starting address of the TCB (parameter register values) for the next DMA operation on the corresponding channel. These registers also control whether the I/O pro- cessor generates an interrupt when the current DMA process ends. Table 2-5.
Page 65: Chaining Dma Status Registers
I/O Processor Chaining DMA Status Registers In the registers shown in Table 2-7 Two status bits are available: one for DMA status and one for chain loading DMA status. Table 2-7. Chaining DMA Status Registers Register Name Width (Bits) Description PPCTL Parallel port control SPMCTLxy...
Page 66: Dma Channel Allocation
IOP Registers Table 2-8. Data Buffers (Cont’d) Buffer Name FIFO Depth Description SPI DMA (DMA only) SPIB DMA (DMA only) IDP_FIFO IDP FIFO Receive MTM read/write DMA only TXPP Parallel Port Transmit RXPP Parallel Port Receive Some data buffers provide debug support to enable the buffer hang disable ) bit.
Page 67: Dma Channel Priority
I/O Processor  DMA channels vary by processormodel. For a breakdown of DMA channels for a particular model, see the ADSP-2136x SHARC Pro- cessor Data Sheet. Also note that each DMA channel has a specific peripheral assigned to it. DMA Channel Priority Table 2-9 shows the paths for internal DMA requests within the I/O processor.
Page 68 DMA Channel Priority Table 2-9. DMA Channel Priorities (Cont’d) Peripheral Control/Status Parameter Data Buffer Description Channel Group Registers Registers Number SPCTL4, IISP4A, IMSP4A, RXSP4A or Serial Port 4A SPMCTL45 CSP4A, CPSP4A TXSP4A Data SPCTL4, IISP4B, IMSP4B, RXSP4B or Serial Port 4B SPMCTL45 CSP4B, CPSP4B TXSP4B...
Page 69 I/O Processor Table 2-9. DMA Channel Priorities (Cont’d) Peripheral Control/Status Parameter Data Buffer Description Channel Group Registers Registers Number IDP_CTL0, IDP_DMA_I4, IDP_FIFO DAI IDP IDP_CTL1, IDP_DMA_M4, Channel 4 IDP_FIFO, IDP_DMA_C4, DAI_STAT IDP_DMA_I4A, IDP_DMA_I4B, IDP_DMA_PC4 IDP_CTL0, IDP_DMA_I5, IDP_FIFO DAI IDP IDP_CTL1, IDP_DMA_M5, Channel 5 IDP_FIFO,...
Page 70: Dma Channel Arbitration Modes
DMA Channel Priority Table 2-9. DMA Channel Priorities (Cont’d) Peripheral Control/Status Parameter Data Buffer Description Channel Group Registers Registers Number MTMCTL IIMTMW, MTM FIFO Memory-to- IMMTMW, memory write CMTMW data MTMCTL IIMTMR, MTM FIFO Memory-to- IMMTMR, memory read CMTMR data DMA Channel Arbitration Modes DMA channel arbitration is the method that the arbiter uses to determine how groups rotate priority with other channels.
Page 71: Rotating Priority By Group
I/O Processor In the fixed priority scheme, the lower indexed peripheral (Table 2-9) has the highest priority. INTERNAL MEMORY I/F ARBITER IOD BUS PERIPHERAL ARBITER Parallel SPIB SPORT0 SPORT1 Port Figure 2-1. I/O Processor Bus Structure Rotating Priority by Group In the rotating priority scheme, the default priorities at reset are the same as that of the fixed priority.
Page 72: Dma Channel Interrupts
DMA Channel Priority When none of the peripherals request bus access, the highest priority peripheral, for example, peripheral 0, is granted the bus. However, this does not change the currently assigned priorities to various peripherals. Within a peripheral group, the priority is highest for the higher indexed peripheral (see Table 2-9).
Page 73: Interrupt Versus Channel Priorities
I/O Processor two interrupts to have priorities that are higher and lower than the serial ports. For more information, see the Program Sequencer “Interrupts and Sequencing” in the SHARC Processor Programming Reference. Interrupt Versus Channel Priorities At default, the DMA interrupt priorities do not match the DMA channel priorities (Table 2-10).
Page 74: Dma Controller Addressing
DMA Channel Priority DMA Controller Addressing Figure 2-2 shows a block diagram of the I/O processor’s address generator (DMA controller). “Standard DMA Parameter Registers” on page 2-6 lists the parameter registers for each DMA channel. The parameter registers are uninitialized following a processor reset. The I/O processor generates addresses for DMA channels much the same way that the Data Address Generators (DAGs) generate addresses for data memory accesses.
Page 75 I/O Processor DMA ADDRESS GENERATOR (INTERNAL ADDRESSES) LOCAL BUS INTERNAL MEMORY MODIFIER INDEX (ADDRESS) ADDRESS POST-MODIFY DMA WORD COUNTER LOCAL BUS – 1 COUNT CHAIN POINTER WORKING REGISTER DMA ADDRESS GENERATOR (EXTERNAL ADDRESSES) LOCAL BUS EXTERNAL EIPP EMPP ECPP MEMORY EXT.
Page 76: Dma Chaining
DMA Chaining • If the I/O processor modifies the internal index register past the maximum 19-bit value to indicate an address out of internal mem- ory, the index wraps around to zero. With the offset for the SHARC processor, the wraparound address is 0x80000. •...
Page 77: Chain Pointer Register
I/O Processor automatically initializes and then begins another DMA transfer when the current DMA transfer is complete. In addition to the standard DMA parameter registers, each DMA channel also has a chain pointer register that points to the next set of DMA parameters stored in the processor’s internal memory.
Page 78: Chain Assignment
DMA Chaining Table 2-12. Chain Pointer Register for SPORTs, SPI, Parallel Port (xCPx) Name Description 18–0 IIx address Next chain pointer address Program controlled interrupt 0 = no interrupt after current TCB 1 = interrupt after current TCB Bit 19 of the chain pointer register is the program controlled interrupt ) bit.
Page 79 I/O Processor T C B 1 TC B 2 I I x I I x I M x I M x If pointing to zero, C P x C P x chain operation ends Figure 2-3. Chaining in the SPI and Serial Ports The address field of the chain pointer registers is only 19 bits wide.
Page 80: Starting Chain Loading
DMA Chaining  Chained DMA operations may only occur within the same chan- nel. The processor does not support cross-channel chaining. Starting Chain Loading A DMA sequence is defined as the sum of the DMA transfers for a single channel, from when the parameter registers initialize to when the count register decrements to zero.
Page 81: Tcb Chain Loading Priority
I/O Processor TCB Chain Loading Priority A TCB chain load request is prioritized like all DMA channels. Therefore, the TCB chain loading request has the same priority level as the DMA channel itself. The I/O processor latches a TCB loading request and holds it until the load request has the highest priority.
Page 82: Configuring Iop/Core Interaction
Configuring IOP/Core Interaction A DMA sequence starts when one of the following occurs. • Chaining is disabled, and the DMA enable bit transitions from low to high. • Chaining is enabled, DMA is enabled, and the chain pointer regis- ter address field is written with a non zero value. In this case, TCB chain loading of the channel parameter registers occurs first.
Page 83: Interrupt-Driven I/O
I/O Processor Interrupt-Driven I/O Programs can check the appropriate status register (for example SPCTL the serial ports) to determine which channels are performing a DMA or chained DMA. All DMA channels can be active or inactive. If a channel is active, a DMA is in progress on that channel.
Page 84: Polling Dma Channel Status
Configuring IOP/Core Interaction processor latches into the , and IRPTL LIRPTL DAI_IRPTL_H DAI_IRPTL_L registers.  The I/O processor only generates a DMA complete interrupt when the channel’s count register decrements to zero as a result of actual DMA transfers. Writing zero to a count register does not generate the interrupt.
Page 85: Standard Dma Status
I/O Processor  Because polling uses processor core resources, it is not as efficient as an interrupt-driven system. Also note that polling the DMA sta- tus registers reduces I/O bandwidth (core higher priority like I/O, “IOP Performance” on page 2-35). The DMA controllers in the ADSP-2136x processor maintain the status information of each channel for the different DMA modes in each of the peripherals registers:...
Page 86: Tcb Storage
TCB Storage TCB Storage This section lists all the different TCB memory allocations used for DMA chaining on the peripherals. Note that all TCBs must be located in inter- nal memory. Serial Port TCB The serial ports support single and chained DMA. Table 2-13 shows the required TCB for chained DMA...
Page 87: Spi Tcb
I/O Processor Table 2-14. Parallel Port TCBs (Cont’d) Address Register CP[18:0] – 0x4 EIPP External Index CP[18:0] – 0x5 EMPP External Modifier CP[18:0] – 0x6 ECPP External Count For more information on programming DMA, refer to the specific periph- eral chapters. ...
Page 88: I/O Processor Register Access
I/O Processor Register Access I/O Processor Register Access All of the I/O processor’s registers are memory-mapped, ranging from address 0x0000 0000 to 0x0003 FFFF. IOP Access Conditions The IOP registers are physically located in two clock domains. 1. Core domain ( )—...
Page 89: Interrupt Latency
I/O Processor The following situations also incur additional stall cycles. 1. Attempting to write to (or read from) a full (or empty) DMA buffer (IDP and SPORT) causes the core to hang indefinitely, unless the (buffer hang disable) bit for that peripheral is set SPCTLx PPCTL IDP_CTL...
Page 90: Tcb Chain Loading Access
I/O Processor Register Access ISR_Routine: R0 = 0x0; dm(SPICTL) = R0; /* disable SPI */ lcntr=10, do (pc,1) until lce; nop; rti; TCB Chain Loading Access Table 2-17 lists the time required to load a specific TCB from the internal memory into the DMA controller.
Page 91: Iop Performance
I/O Processor IOP Performance Since the I/O processor controls the I/O bus, the maximum bandwidth is × 32-bit as shown in achieved with Table 2-17. PCLK Table 2-17. I/O Processor TCB Chain Loading Access Chained TCB Type TCB Size Number of Core Cycles SPI DMA, SPORT DMA Parallel Port DMA...
Page 92 I/O Processor Register Access 2-36 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 93: Memory-To-Memory Port Dma
3 MEMORY-TO-MEMORY PORT DMA Table 3-1 and the following list describe the MTM features. Table 3-1. MTM Port Feature Summary Feature Availability Connectivity Multiplexed Pinout SRU DAI Required SRU DAI Default Routing Interrupt Default Routing Yes (P15I) Protocol Master Capable Slave Capable Transmission Simplex Transmission Half Duplex...
Page 94: Features
Features Table 3-1. MTM Port Feature Summary (Cont’d) Feature Availability Local Memory Clock Operation PCLK Features The memory-to-memory port incorporates: • 2 DMA channels (read and write) • Internal to internal transfers • Data engine for DTCP applications (only for special part numbers) Functional Description The memory-to-memory DMA controller is capable of transferring 64-bit bursts of data between internal memories.
Page 95: Buffer
Memory-to-Memory Port DMA 64-bit data from one internal memory location to another. This register also allows verification of current DMA status during writes and reads. Buffer bit in the register can be set to flush the FIFO and MTMFLUSH MTMCTL reset the read/write pointers.
Page 96: Programming Model
Programming Model Programming Model This data transfer can be set up using the following procedure. 1. Program the DMA registers for both channels. 2. Set (=1) the bit (bit 1) in the register to flush the MTMFLUSH MTMCTL FIFO and reset the read/write pointers. 3.
Page 97 Memory-to-Memory Port DMA /* Fill the source buffer */ lcntr=LENGTH(source), do fill until lce; dm(i0,1)=r0; fill: r0=rot r0 by 1; /* Set the interrupt mask for MTMDMA */ bit set imask MTMI; bit set mode1 IRPTEN; /* Flush the MTMDMA FIFO */ r0=MTMFLUSH;...
Page 98 Programming Example ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 99: Parallel Port
4 PARALLEL PORT The ADSP-2136x processor has a parallel port that allows bidirectional transfers between it and external parallel devices. Using the parallel port bus and control lines, the processor can interface to 8-bit or 16-bit wide external memory devices. The parallel port provides a DMA interface between internal and external memory and has the ability to support core driven data transfer modes (see Table...
Page 100: Features
Features Table 4-1. Parallel Port Feature Summary (Cont’d) Feature Availability DMA Data Access DMA Channels DMA Chaining Interrupt Source Core/DMA Boot Capable Local Memory Clock Operation PCLK/3 Features • Support for standard SRAMs • Interface requires only 16 Pins for address and data •...
Page 101: Pin Descriptions
Parallel Port transfers, and the programming model, with a programming example. Figure 4-1 shows a block diagram of the parallel port. DMD, PMD BUS IOD BUS PARALLEL PORT DATA_RX RXPP PPSI AD15-0 DATA_TX TXPP PPSO ADDR CONTROL STATUS ALE, WR, RD Figure 4-1.
Page 102: Multiplexed Pin Functions
Pin Descriptions Multiplexed Pin Functions The parallel port pins can function as flag pins and the parallel data acqui- sition port pins can function as address pins. For complete information on the pin multiplexing scheme used with these processors, see “Parallel Port Pin Multiplexing”...
Page 103: Data Cycles
Parallel Port pin is active high by default, but can be set active low via the bit (bit 13) in the parallel port control ( ) register. PPALEPL PPCTL  Since polarity is active high by default, systems using parallel port boot mode must use address latching hardware that can pro- cess this active high signal.
Page 104: Data Buffers
Pin Descriptions Data Buffers The parallel port has two data buffers or FIFOs, one each for reads and writes. These are explained the following sections. Read Path The parallel port has a two stage data FIFO for receiving data ( ).
Page 105: Write Path
Parallel Port Write Path The parallel port has a two stage data FIFO for transmitting data ( TXPP The first stage ( ) is a 32-bit register that receives data from the inter- TXPP nal memory via the DMA controller or a core write. The data in TXPP moved to the second 32-bit register, .
Page 106: Operation Modes
Pin Descriptions Operation Modes The external interface follows the standard asynchronous SRAM access protocol. The programmable data cycle duration bit ( ) and optional PPDUR bus hold cycle bit ( ) are provided to interface with memories having different access time requirements. The data cycle duration is pro- grammed via the bit in the register.
Page 107: 16-Bit Mode
Parallel Port are provided through during the second half of the cycle A7–0 AD15–8 when the signal is asserted. The bits provides the data dur- AD7–0 ing the same cycle when is asserted.  Eight-bit mode enables a larger external address range. ADSP-2136x SRAM 16M X 8...
Page 108: Parallel Port Registers
Parallel Port Registers FIFOs and high speed A/D and D/A converters and offers the maximum throughput available on the parallel port (111M byte/sec). In 16-bit mode, 16 bits (maximum) of external address are available through latching the 16 bits of from into the external latch A15–0...
Page 109: Control Register (Ppctl)
Parallel Port Control Register (PPCTL) The parallel port control ( ) register is a memory-mapped register and PPCTL is used to configure and enable the parallel port system. This register also contains status information for the Tx/Rx FIFO, the state of DMA, and for external bus availability.
Page 110: Dma Transfers
Data Transfer Types  Unlike the external port on previous SHARC processors, the ADSP-2136x core cannot directly access the external parallel bus. Instead, the core initializes two registers to indicate the external address and address modifier and then accesses data through inter- mediate registers.
Page 111: Chained Dma Transfers
Parallel Port  Before initializing a chain pointer DMA, it is important that are set to zero. ECPP ICPP Chained DMA Transfers DMA chaining is enabled by setting the (bit 30 in register). PPCHEN PPCTL When chaining is enabled, the next set of DMA parameters are loaded from internal memory after the current DMA cycle and new DMA starts.
Page 112: Core-Driven Transfers
Data Transfer Types • A DMA transfer can be interrupted by resetting the bit, but PPDEN none of the other control settings (except for the bit) should PPEN be changed. If the parallel port remains enabled, then interrupted DMA can be resumed by setting the bit again.
Page 113: Interrupt Driven Accesses
Parallel Port When the core accesses either the registers, the parallel port TXPP RXPP writes/fetches data to/from the specified external address. The details of this functionality and the four main techniques to manage each transfer are detailed in the following sections. In general, core-driven transfers are most advantageous when performing single-word accesses and/or accesses to non-sequential addresses.
Page 114: Status-Driven Transfers (Polling)
Data Transfer Types To facilitate this, the (latch) bit of the register is set to one in LIRPTL every core cycle where the buffer is not full or, in receive mode, in TXPP every core cycle in which the buffer has valid data. When fast 16-bit RXPP wide parallel devices are accessed, there may be as few as ten core cycles between each transfer.
Page 115: Core-Stall Driven Transfers
Parallel Port register—parallel port data cycle duration ( ) and bus hold cycle PPDUR enable ( PPBHC Please refer to “Functional Description” on page 4-4 for further explana- tion of the parallel port bus cycles, but in summary, programs can use the following values.
Page 116: Interrupts
Interrupts • While a DMA transfer is active, the core may only write the PPEN bits of . Accessing any of the DMA parameter reg- PPDEN PPCTL isters or other bits in during an active transfer will cause the PPCTL parallel port to malfunction.
Page 117: Dma Interrupts
Parallel Port DMA Interrupts When DMA is enabled, the maskable inte rrupt occurs when the DMA block transfer has completed (when theDMA internal word count register decrements to zero). ICPP When DMA chaining is enabled and the bit is set in the register, CPPP interrupts are generated whenever the current DMA ends.
Page 118: 8-Bit Access
Throughput As described in “Functional Description” on page 4-4, parallel port accesses require both cycles to latch the external address and addi- tional data cycles to transmit or receive data. Therefore, the throughput on the parallel port is determined by the duration and number of these cycles per word.
Page 119: 16-Bit Access
Parallel Port For example, assume = 0, and the parallel port is in 8-bit PPDUR3 mode. The first byte on a new page takes six peripheral clock cycles (three for the cycle and three for the data cycle), and the next sequential 255 bytes consume three peripheral clock cycles each.
Page 120: 8-Bit Versus 16-Bit Sram Modes
Throughput There should be a correlation between the register values. ECPP ICPP In 16-bit mode, the value should be double that of ECPP ICPP 8-Bit Versus 16-Bit SRAM Modes When considering whether to employ the 16- or 8-bit mode in a particu- lar design, a few key points should be considered.
Page 121: Parallel Port Effect Latency
Parallel Port • When the DMA external modifier is set to zero, ( = 0), the EMPP address does not change after the first cycle, therefore an cycle is only inserted on the first cycle. In this case, the 16-bit port can run twice as fast as the 8-bit port, as the overhead for cycles is zero.
Page 122: Configuring The Parallel Port For Dma
Programming Model Configuring the Parallel Port for DMA Use the following steps to configure the parallel port for a standard DMA transfer. 1. Set (or reset) the bit in the register. Depending on PPTRAN PPCTL whether the operation is write or read, ensure that FIFO is empty and the external interface is idle by reading the status of the bits respectively.
Page 123: Configuring The Parallel Port For Core Access
Parallel Port register. Once the DMA descriptors are fetched, normal DMA exe- cution starts and continues until the register contains all CPPP zeros. Configuring the Parallel Port for Core Access The following steps provide the basic procedure for setting up and initiat- ing a data transfer using the core.
Page 124: Programming Examples
Programming Examples Programming Examples The program shown in Listing 4-1 performs a chained DMA. Listing 4-1. Parallel Port Chained DMA #include <def21364.h> #include <sru21364.h> #include <SRU.h> #define N 5 .section/pm seg_rth; nop; nop; nop; nop; nop; jump start; rti; rti; /* PP interrupt service routine at location 0x00090050 */ .section/pm seg_pp;...
Page 125 Parallel Port r0 = PPEN | PPDUR20 | PPDEN | PPTRAN | PPCHEN | PPBHC; dm(PPCTL) = r0; nop; ADSP-2136x SHARC Processor Hardware Reference 4-27 www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 126 Programming Examples 4-28 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 127: Digital Application Interface
5 DIGITAL APPLICATION INTERFACE The digital application interface (DAI) is comprised of a groups of periph- erals and its respective signal routing unit (SRU). The inputs and outputs of the peripherals are not directly connected to external pins. Rather, the SRUs connect the peripherals to a set ofpins and to each other, based on a set of configuration registers.
Page 128 Features Table 5-1. Routing Unit Feature Summary (Cont’d) Feature Open-drain Three-state High Impedance Programmable Pull-up I/O Level Status Register Interrupts Interrupt Source Core (DAILI or DAIHI) Total Channels Miscellaneous I/O channels Peripheral Channels Clock Operation PCLK/2 The DAI may be used to connect combinations of inputs to combinations of outputs.
Page 129: Functional Description
Digital Application Interface Functional Description Figure 5-1 shows how the DAI pin buffers are connected via the SRU. The DAI is comprised of four primary blocks: • Peripherals (A/B/C) associated with the DAI • A Signal Routing Unit (SRU) • DAI I/O pin buffers •...
Page 130 Functional Description PERIPHERAL INTERNAL CHIP NODE PIN BUFFER ROUTING PERIPHERAL CHIP MISCELLANEOUS BUFFER PERIPHERAL Figure 5-1. DAI Functional Block Diagram Note that Figure 5-1 is a simplified representation of a DAI system. In a real representation, the SRU and DAI would show several types of data being routed from several sources including the following.
Page 131: Signal Naming Conventions
Digital Application Interface • Asynchronous sample rate converters (SRC) • S/PDIF transmitter • S/PDIF receiver • DAI Interrupts (miscellaneous) Signal Naming Conventions Each peripheral associated with the DAI does not have any dedicated I/O pins for off-chip communication. Instead, the I/O pin is only accessible in the chip internally and is known as an internal node.
Page 132: Dai Peripherals
DAI Peripherals DAI Peripherals All peripherals within the DAI that have bidirectional pins that generate a corresponding pin enable signal. Typically, the settings within a periph- eral’s control registers determine if a bidirectional pin is an input or an output, and is then driven accordingly. Both the peripheral control regis- ters and the configuration of the SRU can effect the direction of signal flow in a pin buffer.
Page 133: I/O Pin Buffers
Digital Application Interface For each bidirectional line, the SPORT provides three separate signals. For example, a SPORT clock has three separate SRU connections (instead of one physical pin): • input clock to the SPORT ( SPORTx_CLK_I • output clock of the SPORT ( SPORTx_CLK_O •...
Page 134: Pin Buffers As Signal Output
DAI Peripherals The notation for pin input and o utput connections can be quite confusing at first because, in a typical system, a pin is simply a wire that connects to a device. The manner in which the pins are routed within the SRU requires additional nomenclature.
Page 135 Digital Application Interface either an output or an input. Although the direction of a DAI pin is set simply by writing to a memory-mapped register, most often the pin’s direction is dictated by the designated use of that pin. For example, if the DAI pin were to be hard wired to only the input of another intercon- nected circuit, it would not make se nse for the corresponding pin buffer to be configured as an input.
Page 136: Pin Buffers As Signal Input
DAI Peripherals Pin Buffers as Signal Input When the DAI pin is to be used only as an input, connect the correspond- ing pin buffer enable to logic low as shown inFigure 5-6. This disables the buffer amplifier and allows an off-chip so urce to drive the value present on the DAI pin and at the pin buffer output.
Page 137: Programmable Pull-Up Resistors
Digital Application Interface Programmable Pull-Up Resistors The pin buffer allows systems to attach a pull-up connected to the pad (high impedance) or disconnected (three state). This is controlled through register. DAI_PULLUP Pin Buffers as Open Drain For peripherals like the SPI (multi processing), the bus protocol requires the pin drivers to work in open drain mode (Figure 5-7) for transmit and...
Page 138: Miscellaneous Buffers
DAI Peripherals Miscellaneous Buffers The miscellaneous buffers are used to interconnect signals from different routing groups. These buffers are similar to the DAI pin buffers with three basic differences. 1. Only for internal connections, no pin buffer enable required output always feeds DAI interrupt latch register and MISCxx_O Group F ( PBENx_I...
Page 139: Signal Routing Matrix By Groups
Digital Application Interface Signal Routing Matrix by Groups The SRU can be compared to a set of patch bays, which contains a bank of inputs and a bank of outputs. For each input, there is a set of permissible output options. Outputs can feed to any number of inputs in parallel, but every input must be patched to exactly one valid output source.
Page 140: Dai Group Routing
DAI Peripherals DAI Group Routing Each group has a unique encoding for its associated output signals and a set of configuration registers. For example, DAI group A is used to route clock signals. The memory-mapped registers, , contain bit fields SRU_CLKx corresponding to the clock inputs of various peripherals.
Page 141 Digital Application Interface SPORT5_CLK [32:1] SPORT5_CLK [32:1] SPORT5_CLK [32:1] SPORT5_CLK [32:1] SPORT5_CLK [32:1] SPORT5_CLK [32:1] Figure 5-9. Example DAI SRU Group A Multiplexing (SRU_CLKx) ADSP-2136x SHARC Processor Hardware Reference 5-15 www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 142: Rules For Sru Connections
DAI Peripherals Rules for SRU Connections There are two rules which apply to all routing: 1. Each input must connect to exactly one output 2. An output can feed any number of inputs As an example: • is routed to SPORT0_CLK_O SPORT1_CLK_I •...
Page 143 Digital Application Interface  Note that it is not possible to connect a signal in one group directly to a signal in a different group (analogous to wiring from one patch bay to another). However, group D is largely devoted to routing in this vein.
Page 144 DAI Peripherals Example 1 SPORT0_CLK_I SPORT0_CLK_O SPORT0_CLK_PBEN_O SPORT1_CLK_I SPORT1_CLK_O SPORT1_CLK_PBEN_O Example 2 SPORT0_CLK_I SPORT0_CLK_O SPORT0_CLK_PBEN_O SPORT1_CLK_I DAI_PB04_O SPORT1_CLK_O EXTERNAL PACKAGE ENABLE DAI_PB04_O DAI_PB04_I CONNECTION SPORT1_CLK_PBEN_O PBEN04_I Figure 5-10. SRU Connection to SPORTs (Example 1 and 2) 5-18 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 145 Digital Application Interface Example 3 DAI_PB01_O DAI_PB01_O EXTERNAL PACKAGE ENABLE DAI_PB01_I CONNECTION DAI_PBEN01_I DAI_PB02_O DAI_PB02_O EXTERNAL PACKAGE ENABLE DAI_PB02_I CONNECTION HIGH DAI_PBEN02_I Example 4 DAI_PB01_O DAI_PB01_O EXTERNAL PACKAGE ENABLE DAI_PB01_I CONNECTION PBEN01_I DAI_PB02_O EXTERNAL DAI_PB02_O PACKAGE ENABLE DAI_PB02_I CONNECTION TIMER0_O DAI_PBEN02_I Figure 5-11.
Page 146: Routing Capabilities
DAI Peripherals Routing Capabilities Table 5-1 provides an overview about the different routing capabilities for the DAI unit. The DAI groups allow routing of specific signals like clocks, data, frame syncs. Table 5-2. DAI Routing Capabilities DAI Group Input (xxxx_I) Output (xxxx_O) A–Clocks SPORT5–0...
Page 147: Default Routing
Digital Application Interface Table 5-2. DAI Routing Capabilities (Cont’d) DAI Group Input (xxxx_I) Output (xxxx_O) E– DAI Interrupt 31–22 TIMER2–0 DAI Pin Buffer Miscellaneous FLAG15–10 PDAP output strobe 20–1 Signals TIMER2–0 PCG AB (CLK, FS) Logic level high SPIB (control, data) S/PDIF TX (block start) Logic level low MISCA5–0...
Page 148 Default Routing IDP7-0_DAT_I DIR_I DIT_DAT_I SRC_3-0_DAT_IP_I SRC_3-0_TDM_OP_I SPORT0_DA_I SPORT1_DA_I SPORT1_DA_O SPORT0_DA_O Pin01 Pin05 PBEN_O PBEN_O SPORT0_DB_I SPORT1_DB_I SPORT1_DB_O SPORT0_DB_O Pin02 Pin06 PBEN_O PBEN_O SPORT0_CLK_I SPORT1_CLK_I SPORT0_CLK_O SPORT1_CLK_O Pin03 Pin07 PBEN_O PBEN_O SPORT0_FS_I SPORT1_FS_I SPORT0_FS_O SPORT1_FS_O Pin04 Pin08 PBEN_O PBEN_O Figure 5-12. DAI Default Routing 5-22 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI...
Page 149 Digital Application Interface SPORT2_DA_I SPORT4_DA_I SPORT2_DA_O SPORT4_DA_O Pin09 Pin15 PBEN_O PBEN_O SPORT2_DB_I SPORT4_DB_I SPORT2_DB_O SPORT4_DB_O Pin10 Pin16 PBEN_O PBEN_O SPORT2_CLK_I SPORT4_CLK_I SPORT2_CLK_O SPORT4_CLK_O PBEN_O PBEN_O SPORT2_FS_I SPORT4_FS_I SPORT2_FS_O SPORT4_FS_O PBEN_O PBEN_O SPORT3_CLK_I SPORT5_CLK_I SPORT5_CLK_O SPORT3_CLK_O Pin13 Pin19 PBEN_O PBEN_O SPORT3_FS_I SPORT5_FS_I SPORT3_FS_O SPORT5_FS_O...
Page 150: Interrupt Controller
Interrupt Controller Interrupt Controller The DAI contains a dedicated interrupt controller that signals the core when DAI peripheral events occur. System versus Exception Interrupts Generally, interrupts are classified as system or exception. Exception events include any hardware interrupts (for example, resets) and emula- tion interrupts, math exceptions, and illegal accesses to memory that does not exist.
Page 151: Functional Description
Digital Application Interface Functional Description There are several registers in the DAI interrupt controller that can be con- figured to control how the DAI interrupts are reported to and serviced by the core’s interrupt controller. The DAI contains its own interrupt controller that indicates to the core when DAI audio peripheral related events have occurred.
Page 152: Miscellaneous Interrupts
Interrupt Controller Just as the core has its own interrupt latch registers ( IRPTL LIRPTL the DAI has its own latch registers ( ). When DAI_IRPTL_L DAI_IRPTL_H a DAI interrupt is configured to be high priority, it is latched in the register.
Page 153: Interrupt Events
Digital Application Interface Two registers ( ) replace the DAI periph- DAI_IRPTL_RE DAI_IRPTL_FE eral’s version of the register. As with the register, these DAI IMASK IMASK registers provide a way to specify which interrupts to notice and handle, and which interrupts to ignore. These dual registers function like the register, but with a higher degree of granularity.
Page 154: Servicing Interrupts
Interrupt Controller falling edge of the waveform may be used as an interrupt source as well. Programs may select any of these three conditions: • Latch on the rising edge • Latch on the falling edge • Latch on both the rising and falling edge Table 5-3 shows which interrupts are valid on rising and or falling edges.
Page 155: Debug Features
Digital Application Interface configurable channels ( ). When is read, the DAI_INT[31:0] DAI_IRPTL_H high priority latched interrupts are cleared. When is read, the DAI_IRPTL_L low priority latched interrupts are cleared. For more information, see “DAI Interrupt Controller Registers” on page A-77. ...
Page 156: Loop Back Routing
Debug Features Loop Back Routing The serial peripherals (SPORT and SPI) support an internal loop back mode. If the loop back bit for each peripheral is enabled, it connects the transmitter with the receiver block internally (does not signal off-chip). The SRU can be used for this propose.
Page 157: Programming Model
Digital Application Interface Programming Model As discussed in the previous sections, the signal routing unit is controlled by writing values that correspond to signal sources into bit fields that fur- ther correspond to signal inputs. The SRU is arranged into functional groups such that the registers that are made up of these bit fields accept a common set of source signal values.
Page 158 Programming Model Additional example code is available on the Analog Devices Web site.  There is a macro that has been created to connect peripherals used in a DAI configuration. This code can be used in both assembly and C code. See the...
Page 159: Serial Ports
6 SERIAL PORTS The ADSP-2136x processors have six independent, synchronous serial ports (SPORTs) that provide an I/O interface to a wide variety of periph- eral devices. They are called SPORT0, SPORT1, SPORT2, SPORT3, SPORT4, and SPORT5. Each SPORT has its own set of control registers and data buffers.
Page 160 Table 6-1. Serial Port Feature Summary (Cont’d) Feature SPORT5–0[AB] Access Type Data Buffer Core Data Access DMA Data Access DMA Channels 2 per SPORT DMA Chaining Interrupt Source Core/DMA Boot Capable Local Memory Clock Operation PCLK/4 Bidirectional (transmit or receive) functions provide greater flexibility for serial communications.
Page 161 Serial Ports I/O DATA/DMA BUS PM/DM DATA BUS TXSPxB RXSPxB RXSPxA TRANSMIT DATA RECEIVE DATA TXSPxA RECEIVE DATA BUFFER BUFFER TRANSMIT DATA BUFFER BUFFER HARDWARE HARDWARE COMPANDING COMPANDING (COMPRESSION) (COMPRESSION) SPORTS 1, 3, & 5 ONLY SPORTS 0, 2, & 4 ONLY TRANSMIT RECEIVE RECEIVE SHIFT...
Page 162: Features
Features Features Serial ports offer the following features and capabilities: • Four operation modes (“Selecting Operating Modes” on page 6-18): 1. Standard serial 2. Left-justified 3. I 4. Multichannel • Two bidirectional channels (A and B) per serial port, configurable as either transmitters or receivers.
Page 163 Serial Ports • DMA transfers to and from on-chip and off-chip memory. Each SPORT can automatically receive or transmit an entire block of data both on- and off-chip. • Chained DMA operations for multiple data blocks, see “DMA Chaining” on page 2-20.
Page 164: Pin Descriptions
Pin Descriptions Pin Descriptions Table 6-2 describes pin function. Table 6-2. SPORT Pin Descriptions Internal Nodes Direction Description SPORT5–0_DA_I/O Data Receive or T ransmit Channel A. Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to receive serial data.
Page 165: Sru Sport Receive Master
Serial Ports Table 6-3. SPORT DAI/SRU Signal Connections Internal Node DAI Connection SRU Register Inputs SPORT5–0_CLK_I Group A SRU_CLK1–0 SPORT5–0_FS_I Group C SRU_FS0 SPORT5–0_DA_I Group B SRU_DAT2–0 SPORT5–0_DB_I Outputs SPORT5–0_CLK_O Group A, D SPORT5–0_FS_O Group C, D SPORT5–0_DA_O Group B, D SPORT5–0_DB_O SPORT5–0_CLK_PBEN_O Group F...
Page 166 SRU Configuration and frame sync registers, the reflection sensitivity in these signals can be avoided. Figure 5-10 on page 5-18 shows the default routing of the serial port where the SRU maps: • the signal from the DAI pin ( ) back to the SPORT DAI_PBxx_O clock input (...
Page 167: Functional Description
Serial Ports Functional Description A serial port receives serial data on one of its bidirectional serial data sig- nals configured as inputs, or transmits serial data on the bidirectional serial data signals configured as outputs. It can receive or transmit on both channels simultaneously and unidirectionally, where the pair of data sig- nals can both be configured as either transmitters or receivers.
Page 168: Registers
Registers application program must use the correct serial port data buffers, accord- ing to the value of bit. The bit enables either the transmit SPTRAN SPTRAN data buffers for the transmission of A and B channel data, or it enables the receive data buffers for the reception of A and B channel data.
Page 169 Serial Ports the shaded cells denote that the bits have same function in all operating modes. Table 6-4. SPCTLx Control Bit Comparison Multichannel Mode S and Left-Justified Transmit Control Bits Receive Control Standard Serial Mode Mode (SPORT0, 2, 4) Bits (SPORT1, 3, 5) SPEN_A SPEN_A Reserved...
Page 170: Control Registers (Spctlx)
Registers Table 6-4. SPCTLx Control Bit Comparison (Cont’d) Multichannel Mode S and Left-Justified Transmit Control Bits Receive Control Standard Serial Mode Mode (SPORT0, 2, 4) Bits (SPORT1, 3, 5) SCHEN_B SCHEN_B SCHEN_B SCHEN_B 22 FS_BO Reserved Reserved Reserved 24 SP EN_B SPEN_B Reserved...
Page 171: Data Buffers
Serial Ports registers are described in “SPORT Multichannel Control Registers (SPM- CTLxy)” on page A-43. Data Buffers When programming the serial port channel (A or B) as a transmitter, only the corresponding buffers become active while the TXSPxA TXSPxB receive buffers remain inactive.
Page 172: Transmit Path
Registers Transmit Path If the serial port is configured as a serial transmitter, the data transmitted is written to the buffer. The data is (optionally) com- TXSPxA TXSPxB panded in hardware on the primary A channel (SPORT 0, 2, and 4 only), then automatically transferred to the transmit shift register, because com- panding is not supported on the secondary B channels.
Page 173: Receive Path
Serial Ports been received. The data is then loaded to internal memory by the DMA controller or read directly by the program running on the processor core. Receive Path If the serial data signal is configured as a serial receiver ( = 0), the SPTRAN receive portion of the SPORT shifts in data from the...
Page 174 Registers Bits 31–30 ( and bits 28–27 ( in the registers indi- RXS_A) RXS_B) SPCTLx cate the status of the channel’s receive buffer contents as follows: 00 = buffer empty, 01 = reserved, 10 = buffer partially full, 11 = buffer full. If your program causes the core processor to attempt to read from an empty receive buffer or to write to a full transmit buffer, the access is delayed until the buffer is accessed by the external I/O device.
Page 175: Multichannel Buffer Status
Serial Ports Two complete 32-bit words can be stored in the receive buffer while a third word is being shifted in. The third word overwrites the second if the first word has not been read out (by the processor core or the DMA con- troller).
Page 176: Selecting Operating Modes
Selecting Operating Modes  overflow/underflow status bit in the ROVF_x TUVF_x SPCTLx register becomes fixed in multichannel mode only as either the overflow status bit (SPORTs 1, 3, and 5) or under- ROVF_x TUVF_x flow status bit (SPORTs 0, 2, and 4). Selecting Operating Modes The SPORTs operate in four modes: •...
Page 177: Mode Selection
Serial Ports Mode Selection The serial port operating mode can be selected via the and the SPCTLx SPM- registers. “Serial Port Registers” on page A-30. CTLxy 1. The operating mode bit 11( ) of the register selects OPMODE SPCTLx between I S, left-justified, and standard serial/multichannel mode.
Page 178: Data Word Formats
Data Word Formats Table 6-5. SPORT Operation Modes (Cont’d) SPCTLx Bits SPMCTLxy bits Bit 11 Bit 17 Bit 16 MCEA MCEB OPERATING MODES Multichannel A Channels Multichannel B Channels Multichannel A and B Channels Data Word Formats The format of the data words transmitted over the serial ports is config- ured by the , and bits of the...
Page 179: Endian Format (Lsbf)
Serial Ports Table 6-6. Data Length versus Modes (Cont’d) Mode Word Length (SLEN) bits 8–32 Multichannel 3–32  Although the word lengths can be 3 to 32 bits, transmitting or receiving words smaller than 7 bits at one-fourth the full peripheral clock rate of the serial port may cause incorrect operation when DMA chaining is enabled.
Page 180: Data Type (Dtype)
Data Word Formats The first 16-bit (or smaller) word is right-justified in bits 15–0 of the packed word, and the second 16-bit (or smaller) word is right-justified in bits 31–16. This applies to both receive (packing) and transmit (unpack- ing) operations. Companding can be used with word packing or unpacking.
Page 181: Companding The Data Stream
Serial Ports Transmit or receive sign extension is selected by bit 0 of in the DTYPE register and is common to all transmit or receive channels. If bit 0 SPCTLx is set, sign extension occurs on selected channels that do not have DTYPE companding selected.
Page 182: Companding As A Function
Data Word Formats Companding As a Function Since the values in the transmit and receive buffers are actually com- panded in place, the companding hardware can be used without transmitting (or receiving) any data, for example during testing or debug- ging.
Page 183: Clock Signal Options
Serial Ports Clock Signal Options Each serial port has a clock signal ( ) for transmitting and SPORTx_CLK receiving data on the two associated data signals. The clock signals are configured by the bits of the control registers. A sin- ICLK CKRE SPCTLx...
Page 184: Master Frame Sync
Clock Signal Options CLKDIV = (PCLK/4 x SCLK) – 1 Master Frame Sync The bit field specifies how many transmit or receive clock cycles are FSDIV counted before a frame sync pulse is generated. In this way, a frame sync can initiate periodic transfers.
Page 185: Clock Source (Iclk, Mstr)
Serial Ports data is output. This delay may limit the receiver’s speed of operation. Refer to the ADSP-2136x SHARC Processor Data Sheet for exact timing specifications. Externally-generated late transmit frame syncs also experience a delay from when they arrive to when data is output. This can also limit the max- imum serial clock speed.
Page 186: Frame Sync Options
Frame Sync Options data and frame syncs. Note that transmit data and frame sync signals change their state on the clock edge that is not selected. For example, the transmit and receive functions of any two serial ports connected together should always select the same value for so inter- CKRE nally-generated signals are driven on one edge and received signals are...
Page 187: Internal Versus External Frame Syncs (Ifs, Imfs, Mstr)
Serial Ports must be loaded into the transmit buffer before the previous word is shifted out and transmitted. When is cleared (=0), the corresponding frame sync signal is not required. A single frame sync is required to initiate communications but it is ignored after the first bit is transferred.
Page 188: Logic Level Frame Syncs (Lfs, Lmfs)
Frame Sync Options When is set (=1), the corresponding frame sync signal is generated internally by the processor, and the signal is an output. The SPORTx_FS frequency of the frame sync signal is determined by the value of the frame sync divisor ( ) in the registers.
Page 189: Early Versus Late Frame Syncs (Lafs)
Serial Ports Bit 16 in the registers selects the logic level of the transmit data SPCTLx valid signal ( ) as active low (inverted) if set (=1), or active SPORTx_TDV_O high if cleared (=0). These signals are actually , reconfigured as SPORTx_FS outputs during multichannel operation.
Page 190: Data-Independent Frame Sync (One Channel)
Frame Sync Options checked during the first bit. They do not need to be asserted after that time period. Figure 6-4 illustrates the two modes of frame signal timing. SPORTX_CLK LATE FRAME SYNC EARLY FRAME SYNC DATA Figure 6-4. Normal Versus Alternate Framing Data-Independent Frame Sync (One Channel) When transmitting data out of the SPORT ( = 1), the inter-...
Page 191: Data Independent Frame Sync (Two Channels)
Serial Ports SPORT channel’s transmit buffer. Once data is loaded into the transmit buffer, it is not transmitted until the next frame sync is generated. This mode of operation allows data to be transmitted only at specific times. When = 0 and = 0, a receive signal is generated DIFS...
Page 192: Operating Modes
Operating Modes Note that the SPORT DMA controller typically keeps the transmit buffer full. The application is responsible for filling the transmit buffers with data. Operating Modes The following sections provide detailed information on each operating mode available using the serial ports. It should be noted that many bits in the SPORT registers that control the function of the mode are the same bit but have a different name depending on the operating mode.
Page 193: Clocking Options
Serial Ports • Internal clock enable ( ICLK • Word length ( , 3–32 bits) SLEN • Channel enable ( SPEN_A SPEN_B Clocking Options In standard serial mode, the serial portscan either accept an external serial clock or generate it internally. The bit in the register deter- ICLK...
Page 194: Left-Justified Mode
Operating Modes register. The frame sync can be configured to be active high or SPCTL active low through the bit in the register. The timing between SPCTL the frame sync signal and the first bit of data either transmitted or received is also selectable through the bit in the register.
Page 195: Left-Justified Mode Timing Control Bits
Serial Ports To transmit or receive words continuously in left-justified mode, load the register with the same value as . For example, for 8-bit data FSDIV SLEN words ( = 7), set = 7. SLEN FSDIV Left-Justified Mode Timing Control Bits Several bits in the control register enable and configure left-justi- SPCTLx...
Page 196: I 2 S Mode
Operating Modes SPORTX_CLK SPORTx_FS/WS LEFT-JUSTIFIED MODE LSB n-1 MSB n LSB n MSB n+1 SPORTx_DA/DB DATA SAMPLE n-1 SAMPLE n SAMPLE n +1 Figure 6-5. Word Select Timing in Left-justified Mode S Mode S mode is a three-wire serial bus standard protocol for transmission of two-channel (stereo) pulse code modulation (PCM) digital audio data.
Page 197: I 2 S Mode Timing Control Bits
Serial Ports transmitting the fixed number of words. The transmission of this dummy word toggles , generating an edge. Transmission SPORTx_FS of the dummy word is not required when the I S receiver is a serial port. S Mode Timing Control Bits Several bits in the register enable and configure I S mode...
Page 198 Operating Modes  For I S operation ( = 1), the transfer starts on the left chan- L_FIRST nel first. SPORTx _CLK SPORTx _FS/WS I 2 S MODE LSB n-1 MSB n LSB n MSB n+1 SPORTx_DA/DB DATA WORD n-1 WORD n WORD n+1 RIGHT CHANNEL...
Page 199 Serial Ports 1. The primary A channels of SPORT1, 3, and 5 are capable of expansion only, and the primary A channels of SPORT0, 2, and 4 are capable of compression only. 2. In multichannel mode, SPORT0 and SPORT1 work in pairs; SPORT0 is the transmit channel, and SPORT1 is the receive chan- nel.
Page 200 Operating Modes Table 6-8. TDM Signal Descriptions (Cont’d) Internal Nodes (routed to any Direction Description DAI pin buffer) SPORT01/23/45_TDV_O Transmit d ata valid. SPORT 0 generates the trans- mit data valid pulse (TDV01) for the SPORT0/1 pair. SPORT 2 generates the transmit valid pulse (TDV23) for the SPORT2/3 pair.
Page 201 Serial Ports  SPORTs are paired when multichannel mode is selected. In this mode, transmit/receive directions are fixed where SPORTS 0, 2, and 4 act as transmitters, and SPORTs 1, 3, and 5 act as receivers. Transmit Valid Signals are used as a transmit data valid SPORT0_FS SPORT2_FS SPORT4_FS...
Page 202 Operating Modes • The ) is used as transmit data valid for external TDV01 SPORT0_FS logic. This signal is active only during transmit channels. • The transfer is received on channel 0 (word 0), and transmits on channels 1 and 2 (word 1 and 2) WORD 0 WORD 1 WORD 2...
Page 203 Serial Ports Setting the bits enables multichannel operation for both MCEA MCEB receive and transmit sides of the SPORT0/1, SPORT2/3 or SPORT4/5 pair. Number of Channels (NCH) Select the number of channels used in multichannel operation by using the 7-bit field in the multichannel control register.
Page 204 Operating Modes while disabled channel words are ignored. Up to 128 channels are avail- able for transmitting and receiving. The multichannel selection registers enable and disable individual chan- nels. The registers for each serial port are shown in “SPORT Transmit Select Registers (MTxCSy)”...
Page 205 Serial Ports Receive Selection Registers Setting a particular bit to 1 in the register MR1CS0–3 MR3CS0–3 MR5CS0–3 causes the serial port to receive the word in that channel’s position of the data stream. The received word is loaded into the receive buffer. Clearing the bit in the register causes the serial port to ignore the data.
Page 206 Data Transfer Types When performing core-driven transfers, write to the buffer designated by bit setting in the registers. For DMA-driven transfers, SPTRAN SPCTLx the serial port logic performs the data transfer from internal memory to/from the appropriate buffer depending on the bit setting.
Page 207 Serial Ports receives or starts to transmit a data word. The processor’s on-chip DMA controller handles the DMA transfer, allowing the processor core to con- tinue running until the entire block of data is transmitted or received. Service routines can then operate on the block of data rather than on sin- gle words, significantly reducing overhead.
Page 208 Data Transfer Types Although the DMA transfers are performed with 32-bit words, serial ports can handle word sizes from 3 to 32 bits, with 8 to 32 bits for I S mode. If serial words are 16 bits or smaller, they can be packed into 32-bit words for each DMA transfer.
Page 209 Serial Ports When the count register of an active DMA channel reaches zero (0), the SPORT generates the corresponding interrupt. DMA Chaining Each channel also has a DMA chaining enable bit ( SCHEN_A SCHEN_B in its control register. SPCTLx Each SPORT DMA channel also has a chain pointer register ( CPSPxy register functions are used in chained DMA operations.
Page 210 Interrupts DMA Chain Insertion Mode It is possible to insert a single SPORT DMA operation or another DMA chain within an active SPORT DMA chain. Programs may need to per- form insertion when a high priority DMA requires service and cannot wait for the current chain to finish.
Page 211 Serial Ports “Single Word Transfers” on page 6-47). The priority of the serial port interrupts is shown in Table 2-9 on page 2-11. Multiple interrupts can occur if both SPORTs transmit or receive data in the same cycle. Any interrupt can be masked in the register;...
Page 212 Debug Features Debug Features The following sections provide information on debugging features avail- able with the serial ports. SPORT Loopback When the SPORT loopback bit, (bit 12), is set in the regis- SPMCTLxy ter, the serial port is configured in an internal loopback connection as follows: SPORT0 and SPORT1 work as a pair for internal loopback, SPORT2 and SPORT3 work as pairs, and SPORT4 and SPORT5 work as pairs.
Page 213 Serial Ports the SPORT is configured in Loopback mode. This prevents contention with the internal loopback data transfer.  Only transmit clock and transmit frame sync options may be used in loopback mode—programs must ensure that the serial port is set up correctly in the control registers.
Page 214 Programming Model The SPORT is ready to start transmitting or receiving three serial clock cycles after they are enabled in the control register. No serial clocks SPCTLx are lost from this point on. This delay does also apply in slave mode (external clock/frame sync) for synchronization.
Page 215 Serial Ports Enter DMA Chain Insertion Mode Chain insertion lets the SPORTs insert a single SPORT DMA operation or another DMA chain within an active SPORT DMA chain. 1. Enter chain insertion mode by setting = 0 and = 1 in SDENx SCHENx the channel’s DMA control register.
Page 216 Programming Examples Listing 6-1. SPORT Transmit Using DMA #include <def21364.h> #include <sru21364.h> #include <SRU.h> /* Default Buffer Length */ #define BUFSIZE 10 .SECTION/DM seg_dmda; /* TX Buffers */ .var tx_buf1a[BUFSIZE] = 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888, 0x99999999, 0xAAAAAAAA;...
Page 217 Serial Ports /* TX Transfer Control Blocks */ .var tx_tcb1[4] = 0,BUFSIZE,1,tx_buf1a; .var tx_tcb2[4] = 0,BUFSIZE,1,tx_buf1b; /* RX Transfer Control Blocks */ .var rx_tcb1[4] = 0,BUFSIZE,1,rx_buf0a; .var rx_tcb2[4] = 0,BUFSIZE,1,rx_buf0b; /* Main code section */ .global _main; .SECTION/PM seg_pmco; _main: r0 = 0;...
Page 218 Programming Examples SDEN_A| /* Enable Channel A DMA */ SCHEN_A| /* Enable Channel A DMA Chaining */ IFS| /* Internally-generated Frame Sync */ ICLK; /* Internally-generated Clock */ dm(SPCTL1) = ustat4; /* Configure SPORT0 as a receiver */ /* externally generating clock and frame sync */ r0 = 0x0;...
Page 219 Serial Ports /* Next TCB location for tx_tcb1 is tx_tcb2 */ /* Mask the first 19 bits of the TCB location */ r0 = (tx_tcb2 + 3) & 0x7FFFF; dm(tx_tcb1) = r0; /* Initialize SPORT DMA transfer by writing to the CP reg */ dm(CPSP1A) = r0;...
Page 220 Programming Examples bit set mode1 CBUFEN; /* enable circular buffers */ /* SPORT Loopback: Use SPORT2 as RX & SPORT3 as TX */ /* Initially clear SPORT control registers */ r0 = 0x00000000; dm(SPCTL2) = r0; dm(SPCTL3) = r0; dm(SPMCTL23) = r0; /* Set up DAG registers */ i4 = tx_buf2a;...
Page 221 Serial Ports dm(SPCTL2) = ustat4; /* Configure SPORT3 as a receiver */ /* externally generating clock and frame sync */ r0 = 0x0; dm(DIV3) = R0; ustat3 = SPEN_A| /* Enable Channel A */ SLEN32| /* 32-bit word length */ FSR;...
Page 222 Programming Examples 0x77777777, 0x88888888, 0x99999999, 0xAAAAAAAA; /*Receive buffer*/ .var rx_buf4a[BUFSIZE]; /* Main code section */ .global _main; .SECTION/PM seg_pmco; _main: /* SPORT Loopback: Use SPORT4 as RX & SPORT5 as TX */ /* initially clear SPORT control register */ r0 = 0x00000000; dm(SPCTL4) = r0;...
Page 223 Serial Ports /* SPORT 4 Internal DMA memory access modifier */ r0 = 1; dm(IMSP4A) = r0; /* SPORT 4 Number of DMA5 transfers to be done */ r0 = length(rx_buf4a); dm(CSP4A) = r0; /* set internal loopback bit for SPORT4 & SPORT5 */ bit set ustat3 SPL;...
Page 224 Programming Examples 6-66 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 225 7 SERIAL PERIPHERAL INTERFACE PORTS The ADSP-2136x processors are equipped with two synchronous serial peripheral interface ports that are compatible with the industry-standard serial peripheral interface (SPI). Each SPI port also has its own set of regis- ters (the secondary register set contains a B as in ).
Page 226 Features Table 7-1. SPI Port Feature Summary (Cont’d) Feature SPIB Transmission Simplex Transmission Half Duplex Transmission Full Duplex Yes (Core and DMA) Yes (Core and DMA) Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Interrupt Source Core/DMA Core/DMA...
Page 227 Serial Peripheral Interface Ports • Master or slave booting from a master SPI device. See “SPI Port Booting” on page 14-38. • DMA capability to allow transfer of data without core overhead. Note the SPI interface does not support daisy chain operation, where the pins are internally connected through a FIFO, allowing MOSI MISO...
Page 228 SRU Programming Table 7-2. SPI Pin Descriptions (Cont’d) Internal Node Type Description SPI_MISO_I/O SPI Master In Slave Out. This data line transmits the SPIB_MISO_I/O output data from the slave device and receives the input data to the master device. This data is shifted out from the MISO pin of the slave and shifted into the MISO input of the master.
Page 229 Serial Peripheral Interface Ports Table 7-3. SPI DAI/SRU Signal Connections (Cont’d) Internal Node DAI Group SRU Register Outputs SPIB_CLK_O Group D SPIB_MOSI_O SPIB_MISO_O SPIB_FLG3–0_O SPIB_CLK_PBEN_O Group F SPIB_MOSI_PBEN_O SPIB_MISO_PBEN_O SPIB_FLG3–0_PBEN_O Since the SPI supports a gated clock, it is recommended that programs enable the SPI clock output signal with its related pin buffer enable.
Page 230 Functional Description using the pin. It transmits requested data out of the transmit shift MOSI register using the pin. MISO SPIDS MOSI MISO SPICLK FLAGx SPI CONTROL/STATUS RXSR SHIFT REGISTER TXSR SHIFT REGISTER 8/16/32 BITS 8/16/32 BITS TXSPI REGISTER RXSPI REGISTER 1 DEEP 1 DEEP DMA FIFO...
Page 231 Serial Peripheral Interface Ports Once a full data word has been received in the receive shift register, the data is automatically transferred into , from which the data can be RXSPIx read. When the processor is in SPI master mode, programmable flag pins provide slave selection.
Page 232 Functional Description Figure 7-3 shows an example SPI interface where the SHARC processor is the SPI master. With the SPI interface, the processor can be directed to alter the conversion resources, mute the sound, modify the volume, and power down the AD1855 stereo DAC. AD1855 STEREO 96 kHz DAC ADSP-2136x...
Page 233 Serial Peripheral Interface Ports Slaves can be thought of as input/output devices of the master. The SPI does not specify a particular higher-level protocol for bus mastership. In some applications, a higher-level protocol, such as a command-response protocol, may be necessary. Note that the master must initiate the frames for both its’...
Page 234 Register Descriptions Another feature is implemented to trouble shoot the bus mastership pro- tocol. If a recent SHARC bus master receives an invalidly asserted SPIDS signal, it triggers an error handling scenario using the bit ( SPIMME for DMA) and bit to reconfigure the SPI to slave mode, and jump ISSEN into an ISR.
Page 235 Serial Peripheral Interface Ports information, see “SPI Control Registers (SPICTL, SPICTLB)” on page A-14. Transfer Initiate Mode (TIMOD) When the processor is enabled as a master, the initiation of a transfer is defined by the bits (1–0). Based on these two bits and the status of TIMOD the interface, a new transfer is started upon either a read of the reg-...
Page 236 Register Descriptions Table 7-4. Transfer Initiation (Cont’d) TIMOD Function Transfer Initiated Upon Action, Interrupt Initiate new multiword trans- If chaining is disabled, the SPI interrupt Transmit fer upon write to DMA enable is latched in the cycle when the DMA Receive with bit.
Page 237 Serial Peripheral Interface Ports only one slave can be enabled to se nd data back to the master. The ( D MISO bit disables as an output. MISO Word Lengths (WL) The SPI port can transmit and receive the word widths described in the following sections.
Page 238 Register Descriptions For example, if the processor executes the following instructions: r0 = 0x12345678 dm(TXSPI) = r0; the SPI port transmits 0x5678 When receiving, the SPI port packs the16-bit word to the lower 32 bits of buffer while the upper bits in the register are zeros. RXSPI For example, if an SPI host sends the processor the 32-bit word , the processor receives the following words:...
Page 239 Serial Peripheral Interface Ports For example, a 16-bit transfer with the LSB first is one possible configuration. The clock polarity and the clock phase should be identical for the master device and slave devices involved in the communication link. The transfer format from the master may be changed between transfers to adjust to var- ious requirements of a slave device.
Page 240 Register Descriptions SPI Transfer Protocol for CPHASE = 0 CLOCK CYCLE NUMBER SPICLK CLKPL=0 (SPI MODE 0) SPICLK CLKPL=1 (SPI MODE 2) MOSI FROM MASTER MISO FROM SLAVE SPIDS FROM MASTER * = UNDEFINED SPI Transfer Protocol for CPHASE = 1 CLOCK CYCLE NUMBER SPICLK...
Page 241 Serial Peripheral Interface Ports Open Drain Mode (OPD) In a multimaster or multislave SPI system, the data output pins ( MOSI ) can be configured to behave as open drain drivers to prevent conten- MISO tion and possible damage to pin drivers. An external pull-up resistor is required on both the pins when this option is selected.
Page 242 Register Descriptions Packing (PACKEN) In order to communicate with 8-bit SPI devices and store 8-bit words in internal memory, a packed transfer feature is built into the SPI port. Pack- ing is enabled through the bit (15). The SPI unpacks data when it PACKEN transmits and packs data when it receives.
Page 243 Serial Peripheral Interface Ports Multi Master Error (MME) bit (1) is set when the input pin of a device that is enabled SPIDS as a master is driven low by some other device in the system. This occurs in multimaster systems when another device is also trying to be the master. To enable this feature, set the bit in the register.
Page 244 Register Descriptions , in the register prior to configuring the SPI port. See the FLAG3–0 FLAGS FLAGs value register description in the SHARC Processor Programming Reference “Registers” appendix. Transmission Error Bit (TUNF) bit (2) is set when all of the conditions of transmission are met TUNF and there is no new data in is empty).
Page 245 Serial Peripheral Interface Ports BAUD Rate Register (SPIBAUDx) For master devices, the clock rate is determined by the 15-bit value of the baud rate registers ( ) as shown in Table 7-5. For slave devices, SPIBAUDx the value in the register is ignored.
Page 246 Data Transfer Types Core Transfers For core-driven SPI transfers, the software has to read from or write to the registers respectively to control the transfer. It is RXSPIx TXSPIx important to check the buffer status before reading from or writing to these registers because the core does not hang when it attempts to read from an empty buffer or write to a full buffer.
Page 247 Serial Peripheral Interface Ports DMA interrupt errors. Guidelines that programs should follow when per- forming DMA transfers over the SPI include: • Do not write to the registers during an active SPI transmit TXSPIx DMA operation because DMA data will be overwritten. •...
Page 248 Data Transfer Types Slave DMA Transfer Preparation When enabled as a slave, the device prepares for a new transfer according to the function and actions described in Table 7-4 on page 7-11. The following steps illustrate the SPI receive or transmit DMA sequence in an SPI slave in response to a master command: 1.
Page 249 Serial Peripheral Interface Ports transmit port operates according to the state of the SENDZ in the registers. SPICTLx = 1 and the DMA buffer is empty, the device SENDZ repeatedly transmits zeros on the pin. If = 0 and MISO SENDZ the DMA buffer is empty, it repeatedly transmits the last word transmitted before theDMA buffer became empty.
Page 250 Data Transfer Types  Writing an address to the , registers does not begin a CPSPIx chained DMA sequence unless the IISPI IMSPI CSPI IISPIB , and registers are initialized, SPI DMA is enabled, IMSPIB CSPIB the SPI port is enabled, and SPI DMA chaining is enabled. Core and DMA Transfers When the SPI DMA engine is configured for transmitting: 1.
Page 251 Serial Peripheral Interface Ports However, when an SPI communication link consists of: 1. A single master and a single slave, CPHASE 3. The slave’s slave select input is tied low Then the program can change the SPI confi g uration. In this case, the slave is always selected.
Page 252 Interrupts To maintain software compatibility with other SPI devices (HC-11), the SPI transfer finished bit ( ) is also available for polling. This bit may SPIF have slightly different behavior from that of other commercially available devices. For a slave device, is set at the same time as .
Page 253 Serial Peripheral Interface Ports During DMA driven transfers, an SPI interrupt is triggered: 1. At the completion of a single DMA transfer 2. At the completion of a number of DMA sequences (if DMA chain- ing is enabled) 3. When a DMA error has occurred Note that the register must be initialized properly to enable DMA SPIDMAC...
Page 254 Interrupts Internal Transfer Completion The DMA interrupts indicate DMA completion status and DMA error status. These interrupts are latched in the core when the DMA count reaches zero. For a chained DMA of blocks ( = 1), the interrupt is generated when- ever the DMA count reaches zero DMA Error Interrupts bits of the...
Page 255 Serial Peripheral Interface Ports Without disabling the SPI: 1. Disable DMA and clear the FIFO by writing 0x80 to the SPIDMAC register. This ensures that any data from a previous DMA opera- tion is cleared before configuring a new DMA operation. 2.
Page 256 Debug Features This is shown as: T3 = 0.5 SPI clock period T4 = 1.5 SPI clock period + T3 For a master device with = 0 or = 1, this means that the CPHASE CPHASE slave-select output is inactive (high) for at least one-half the SPICLK period.
Page 257 Serial Peripheral Interface Ports Internal Loopback Mode In this mode different types of loopback are possible since there is only one DMA channel available: • Core receive and transmit transfers • Transmit DMA and core receive transfers • Core Transmit and DMA receive transfers To loop data back from , the pin is internally discon-...
Page 258 Programming Model port, programs should specify which of the slave-select signals to use, setting one or more of the required SPI flag select bits ( DSxEN in the registers. SPIFLGx 2. Write to the registers, enabling the device as SPICTLx SPIBAUDx a master and configuring the SPI system by specifying the appro- priate word length, transfer format, baud rate, and other necessary...
Page 259 Serial Peripheral Interface Ports • If = 0 and the transmit buffer isempty, the device repeatedly SENDZ transmits the last word transmitted before the transmit buffer became empty. • If = 1 and the receive buffer is full, the device continues to receive new data from the pin, overwriting the older data in MISO...
Page 260 Programming Model If the transmit buffer remains empty, or the receive buffer remains full, the devices operate according to the states of the bits in the SENDZ registers. SPICTLx • If = 1 and the transmit buffer is empty, the device repeatedly SENDZ transmits zero’s on the pin.
Page 261 Serial Peripheral Interface Ports 4. For a single DMA, define the parameters of the DMA transfer by writing to the , and registers. For DMA IISPIx IMSPIx CSPIx chaining, write the chain pointer address to the registers. CPSPIx Write to the SPI DMA configuration registers, ( ), to specify the SPIDMACx DMA direction (...
Page 262 Programming Model operation should be ignored. The data in the register is not RXSPI intended to be used, and the (bits 28–27 and 31–30 in the SPICTLx registers) and bits (bits 26 and 29) should be ignored. The SPISTAT ROVF overrun condition cannot generate an error interrupt in this mode.
Page 263 Serial Peripheral Interface Ports To configure for slave mode DMA: 1. Write to the register to make the mode of the serial link SPICTLx the same as the mode that is set up in the SPI master. Configure field to select transmit or receive DMA mode TIMOD = 10).
Page 264 Programming Model 5. Select which flag to use as the SPI slave select signal in the SPIFLG register. 6. Configure and enable the SPI port with the , SPICTLB SPICTL registers. 7. Configure the DMA settings for the entire sequence, enabling DMA and DMA chaining in the register.
Page 265 Serial Peripheral Interface Ports shift register. DMA interrupts are latched when the I/O processor moves the last word from memory to the peripheral. For the SPI, this means that the SPI “DMA complete” interrupt is latched when there are six words remaining to be transmitted (four in the FIFO, one in the buffers, TXSPIx...
Page 266 Programming Model 3. Clear all errors by writing to the W1C-type bits in the SPISTATx registers. This ensures that no interrupts occur due to errors from a previous DMA operation. 4. Reconfigure the registers and enable the SPI ports. SPICTLx 5.
Page 267 Serial Peripheral Interface Ports With disabled SPI: 1. Write 0x00 to the registers to disable SPI. Disabling SPI SPICTLx also clears the register contents and the buffer RXSPIx TXSPIx status. 2. Disable DMA and clear the DMA FIFO by writing 0x80 to the registers.
Page 268 Programming Examples 4. Reconfigure the registers to remove the clear condition on SPICTLx registers. TXSPIx RXSPIx 5. Configure DMA by writing to the DMA parameter registers (described in “DMA Channel Priority” on page 2-11) and the registers using the bit (bit 0). SPIDMACx SPIDEN Programming Examples...
Page 269 Serial Peripheral Interface Ports .var tx_buf[BUFSIZE] = 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888, 0x99999999, 0xAAAAAAAA; /* Main code section */ .global _main; .SECTION/PM seg_pmco; _main: /* Init SPI MASTER TX */ r0=0; dm(SPICTL) = r0; dm(SPIFLG) = r0; /* Set up DAG registers */ i4 = tx_buf;...
Page 270 Programming Examples dm(SPIBAUD) = ustat3; /* Set up loop to transmit data */ lcntr = LENGTH(tx_buf), do (pc,4) until lce; /* Retrieve data using DAG1 and send TX via SPI */ r0 = dm(i4,m4); dm(TXSPI) = r0; _main.end: jump (pc,0); Listing 7-2.
Page 271 Serial Peripheral Interface Ports ustat3 = DMISO| /* Disable MISO on transfers */ WL32| /* 32-bit words */ SPIMS| /* Master mode (internal SPICLK) */ SPIEN| /* Enable SPI port */ TIMOD2; /* Initialize SPI port to begin transmitting when DMA is enabled */ dm(SPICTL) = ustat3;...
Page 272 Programming Examples _main: /* clear SPI settings */ r0 = 0; dm(SPICTL) = r0; dm(SPIFLG) = r0; dm(SPIDMAC) = r0; /* setup first DMA in chain */ ustat3 = 8; dm(CSPI) = ustat3; /* count = 8 words */ ustat3 = 1; dm(IMSPI) = ustat3; /* step size = 1 */ ustat3 = dest_bufA;...
Page 273 Serial Peripheral Interface Ports SPICHEN| /* enable DMA chaining */ SPIDEN; /* enabling DMA initiates the transfer */ dm(SPIDMAC) = ustat3; /* 1st DMA starts when a valid address is written to CPSPI*/ ustat3 = (0x7FFFF&(first_tcb+3)); dm(CPSPI) = ustat3; /* point to tcb_A */ _main.end: jump(pc,0);...
Page 274 Programming Examples 7-50 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 275 8 INPUT DATA PORT The Input Data Port (IDP) compromises two units: the serial input port (SIP) and the parallel data acquisition port (PDAP). Located inside the DAI of the SHARC processor, it provides an efficient way of transferring data from DAI pin buffers, the parallel port, the asynchronous sample rate converters (ASRC) and the S/PDIF transceiver to the internal memory of SHARC.
Page 276 Features Table 8-1. IDP Port Feature Summary (Cont’d) Feature PDAP Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Interrupt Source Core/DMA (DAI) Core/DMA (DAI) Boot Capable Local Memory Clock Operation PCLK/4 PCLK/4 •...
Page 277 Input Data Port Functional Description The IDP has eight serial input ports (SIPs) and one parallel data acquisi- tion port (PDAP). There is a central 8 x 32 FIFO with 8 input channels where data from all the eight SIPs an d PDAP are collected. Transfers from this FIFO to internal memory can be performed either via DMA or by interrupts driven by the core.
Page 278 Serial Input Port DATA PDAP CONTROL CORE IDP_CLK_0 SIP0 IDP_FS_0 SERIAL/PARALLEL IDP_DAT_0 32-BIT CONVERSION IDP_FIFO INTERNAL IDP_CLK_x 8 x 32-BIT MEMORY SIPx (x = 6 - 1) IDP_FS_x SERIAL/PARALLEL IDP_DAT_x 32-BIT CONVERSION IDP_CLK_7 SIP7 IDP_FS_7 SERIAL/PARALLEL IDP_DAT_7 32-BIT CONVERSION Figure 8-1. Input Data Port Serial Input Port The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs.
Page 279 Input Data Port Pin Descriptions Table 8-2 provides descriptions of the pins used for the serial interface port. Table 8-2. SIP Pin Descriptions Internal Node Description IDP7–0_CLK_I Serial Input Port Receive Clock Input. This signal must be generated externally and comply to the supported input formats.
Page 280 Serial Input Port Input Data Formats An audio signal that is normally 24 bits wide is contained within the 32-bit word. An additional four bits ar e available for status and formatting data (compliant with the IEC 90958, S/PDIF, and AES3 standards). An additional bit identifies the left-right one-half of the frame.
Page 281 Input Data Port I 2 S AND LEFT-JUSTIFIED FORMAT 24-BIT AUDIO DATA 3 BITS VALIDITY BIT IDP CHANNEL USER DATA L/R BIT CHANNEL STATUS BLOCK STATUS RIGHT-JUSTIFIED FORMAT, 24-BIT DATA WIDTH 4 BITS, 3 BITS 24 BITS AUDIO DATA SET TO ZERO CHANNEL RIGHT-JUSTIFIED FORMAT, 20-BIT DATA WIDTH...
Page 282 Serial Input Port The polarity of left-right encoding isindependent of the serial mode frame sync polarity selected in for that channel (Table 8-4). Note that IDP_SMODE S mode uses a low frame sync (left-right) signal to dictate the first (left) channel, and left-justified mode uses a frame sync (left-right) signal HIGH...
Page 283 Input Data Port Register Descriptions This section provides information on the IDP control and status registers. Complete bit information can be found at “Input Data Port Registers” on page A-47. Control Registers (IDP_CTLx) The ADSP-2136x SHARC processors have a new IDP control register .
Page 284 Parallel Data Acquisition Port (PDAP) high then clock edge is masked for data latching. It supports four types of data packing mode selected by bits in the register. MODE IDP_PP_CTL Port Selection The input to channel 0 of the IDP is multiplexed, and may be used either in the serial mode or in a direct parallel input mode.
Page 285 Input Data Port Pin Descriptions PDAP signals include 20 data signals and three control signals with one clock ( ), one hold ( ), and one PDAP data request PDAP_CLK_I PDAP_HOLD_I strobe ( ) signal. The (bit 26 of PDAP_STRB_O IDP_PP_SELECT IDP_PP_CTL register) decides the mapping of these signals.
Page 286 Parallel Data Acquisition Port (PDAP) SRU Programming Table 8-5 shows the signal connections when using the PDAP on the DAI pins. Table 8-5. PDAP DAI/SRU Signal Connections Internal Node DAI Connection SRU Register Inputs PDAP_CLK_I G roup A SRU_CLK2 PDAP_HOLD_I Group C SRU_FS2 DAI_PB20–1_I...
Page 287 Input Data Port IDP_PP_SELECT IDP_Pxx_MASK IDP_PDAP_PACKING IDP_PDAP_EN AD[15:0] [19:4] PACKING DAI PINS MASK UNIT [20:5] DAI PINS FIFO [3:0] [4:1] SERIAL INPUT Figure 8-7. Parallel Data Acquisition Port (PDAP) Functions PDAP Data Packing Multiple latched parallel sub word samples may be packed into 32-bit words for efficiency.
Page 288 Parallel Data Acquisition Port (PDAP) Mode 10 (Packing by 2) Mode 10 moves data in two cycles. Each input word can be up to 16 bits wide. • On clock edge 1, bits 19–4 are moved to bits 15–0 (16 bits) •...
Page 289 Input Data Port • On clock edge 3, bits 19–12 are moved to bits 23–16 • On clock edge 4, bits 19–12 are moved to bits 31–24 This mode sends one packed 32-bit word to FIFO for every four input clock cycles—the DMA transfer rate is one-quarter the PDAP input clock rate.
Page 290 Parallel Data Acquisition Port (PDAP) PDAP_CLK_I PDAP_HOLD_I PDAP DATA PDAP_STROBE_O PDAP_CLK_I PDAP_HOLD_I PDAP DATA PDAP_STROBE_O Figure 8-9. PDAP Hold Input (Mode = 11, No Packing) PD A P_ C LK _ I PD A P_ HO LD _ I P DA P D AT A P DA P_ ST R OB E_ O PD AP _C L K _I P D AP _H OL D _I...
Page 291 Input Data Port PDAP_ CLK_ I PDAP_ HO LD_ I P DAP DATA P DAP_ STROBE_ O PDAP _CLK_I P DAP _HOLD_I PDAP DATA PDAP_S TRO BE _O Figure 8-11. PDAP Hold Input (Mode = 00, Pack by 4)) As shown in the figures, are driven by the inac- PDAP_DATA PDAP_HOLD...
Page 292 Data Transfer Types Data Transfer Types The data from each of the eight IDP channels is inserted into an eight reg- ister deep FIFO, which can only be tran sferred to the core’s memory space sequentially. Data is moved into the FIFO as soon as it is fully received. One of two methods can be used to move data from the IDP FIFO to internal memory: •...
Page 293 Input Data Port The three LSBs of FIFO data are the encoded channel number. These are transferred “as is” for this mode. These bits can be used by software to decode the source of data.  The maximum data transfer width to internal memory is 32-bits, as in the case of PDAP data or I S and left-justified modes in single channel mode using 32 bits of data.
Page 294 Data Transfer Types Standard DMA The eight DMA channels each have an index, modify, and count register used for standard DMA. These registers are described below. • Internal index registers ( ). Index registers provide an IDP_DMA_Ix internal memory address, acting as a pointer to the next internal memory location where data is to be written.
Page 295 Input Data Port The IDP DMA parameter registers are described below. • Internal index registers ( IDP_DMA_Ix IDP_DMA_IxA IDP_DMA_IxB Index A/B registers provide an internal memory address, acting as a pointer to the next internal memory location where data is to be written.
Page 296 Data Transfer Types For serial input channels, data is received in an alternating fashion from left and right channels. Data is not pushed into the FIFO as a full left/right frame. Rather, data is transferred as alternating left/right words as it is received. For the PDAP and32-bit (non-audio) serial input, data is transferred as packed 32-bit words.
Page 297 Input Data Port set, the bits clear once the required number of data trans- IDP_DMAx_STAT fers takes place. For more information, see “Digital Applications Interface Status Register (DAI_STAT)” on page A-79.  Note that when a DMA channel is not used (that is, parameter reg- isters are at their default values), the DMA channel’s corresponding bit is cleared (= 0).
Page 298 Debug Features At the end of the DMA transfer for individual channels, interrupts are generated. These interrupts are generated after the last DMA data from a particular channel has been transferred to memory. These interrupts ) are mapped from the bits 17–10 in the regis- IDP_DMAx_INT DAI_IRPTL_x...
Page 299 Input Data Port Buffer Hang Disable bit in is used for buffer hang disable control. When IDP_BHD IDP_CTL0 there is no data in the FIFO, reading the register causes the core IDP_FIFO to hang. This condition continues until the FIFO contains valid data. Set- ting the bit (= 1) prevents the core from hanging on reads from IDP_BHD...
Page 300 IDP Effect Latency IDP Effect Latency The IDP is ready to start receiving data one serial clock cycle ( ) after SCLK it is enabled by setting bit. No edges are lost from this point IDP_EN LRCLK Disabling IDP DMA by resetting the bit requires 1 IDP_DMA_EN PCLK...
Page 301 Input Data Port Starting Core Interrupt-Driven Transfer To start a core interrupt-driven data transfer: 1. Clear the FIFO by setting (= 1) bit (bit 31 in the IDP_FFCLR register). IDP_CTL1 2. Keep the clock and frame sync inputs of all serial inputs and/or the PDAP connected to low by setting proper values in the SRU registers.
Page 302 Programming Model 3. Keep the clock and the frame sync input of the serial inputs and/or the PDAP connected to low, by setting proper values in the SRU registers. 4. Refer to “Setting Miscellaneous Bits” above. 5. Enable the channel’s bit settings.
Page 303 Input Data Port 5. Connect all of the inputs to the IDP by writing to the SRU registers. 6. Enable the channel’s IDP_ENx IDP_DMA_ENx IDP_PINGx settings. 7. Start DMA by setting: • The bit (bit 31 in register if the IDP_PDAP_EN IDP_PP_CTL PDAP is required).
Page 304 Programming Model 3. The program clears (= 0) the channel’s bit in the IDP_DMA_ENx register which has finished. IDP_CTL1 4. Reprogram the DMA registers for finished DMA channels. More than one DMA channel may have completed during this time period. For each channel, a bit is latched in the DAI_IRPTL_L registers.
Page 305 Input Data Port Programming Example Listing 8-1 shows a data transfer using an interrupt service routine (ISR). The transfer takes place through the digital applications interface (DAI). This code implements the algorithm outlined in “Data Transfer Types” on page 8-18. Listing 8-1.
Page 306 Programming Example SRU(DAI_PB11_O, IDP0_DAT_I); SRU(DAI_PB12_O, IDP0_FS_I); /* Pin buffers 10, 11 and 12 are always being used as */ /* inputs. Tie their enables to LOW (never driven). */ /* Connect PBEN10_I to LOW */ /* Connect PBEN11_I to LOW */ /* Connect PBEN12_I to LOW */ SRU(LOW, PBEN10_I);...
Page 307 Input Data Port initIDP.end: IDP_ISR: i0 = OutBuffer; m0 = 1; l0 = 0; LCNTR = 7, DO RemovedFromFIFO UNTIL LCE; r0 = dm(IDP_FIFO); dm(i0,m0) = r0; RemovedFromFIFO: RTI; IDP_ISR.end: ADSP-2136x SHARC Processor Hardware Reference 8-33 www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 308 Programming Example 8-34 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 309 9 PERIPHERAL TIMERS In addition to the internal core timer, (using the pin as output), TMREXP the ADSP-2136x processor processors contain identical 32-bit peripheral timers that can be used to interface with external devices. Each timer can be individually configured in three operation modes. Features The peripheral timers have the features shown in Table...
Page 310 Features Table 9-1. Timers Feature Summary (Cont’d) Feature Timer2–0 Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Interrupt Source Core Boot Capable Local Memory Clock Operation PCLK • Independent general-purpose timers • Three operation modes (PWM, Width capture, external watchdog) •...
Page 311 Peripheral Timers PMD/DMD BUS PERIOD BUFFER WIDTH BUFFER (32 BIT) (32 BIT) TIMERx_PERIOD TIMERx_WIDTH (32 BIT) (32 BIT) TIMERx_COUNTER (32 BIT) EXPIRE EQUAL? EQUAL? CONTROL CONTROL LOGIC LOGIC (READ ONLY) Figure 9-1. Timer Block Diagram Pin Descriptions The timer has only one pin which acts as input or output based on the timer mode as shown in Table 9-2.
Page 312 SRU Programming Table 9-2. Peripheral Timer Pin Descriptions Internal Node Type Description TIMER2–0_O Timer Signal. This output is active driven in pulse width modulation (PWM out mode). TIMER2–0_PBEN_O Timer Pin Buffer Enable Output Signal. This output is only driven in PWM out mode. SRU Programming Since the timer has operation modes for input (capture and external clock mode) and output (PWM out mode), it requires bidirectional junctions.
Page 313 Peripheral Timers functions, each timer has four, 32-bit registers. The registers for each timer are: • Timer x control ( ) register TMxCTL • Timer x word count ( ) register TMxCNT • Timer x word period ( ) register TMxPRD •...
Page 314 Register Descriptions Counter Registers (TMxCNT) When disabled, the timer counter retains its state. When re-enabled, the timer counter is re initialized from the period/width registers based on configuration and mode. The timer counter value should not be set directly by the software. It can be set indirectly by initializing the period or width values in the appropriate mode.
Page 315 Peripheral Timers ues must be updated “on the fly” since the period and width (duty cycle) change simultaneously. To insure period and width value concurrency, a 32-bit period buffer and a 32-bit width buffer are used. During the pulse width and period capture (WDTH_CAP) mode, both the period and width values are captured at the appropriate time.
Page 316 Operation register. To enable all three timers in parallel, set all the TMSTAT TIMxEN bits in the register. TMSTAT Before enabling a timer, always program the corresponding timer’s config- uration ( ) register. This register defines the timer’s operating mode, TMxCTL the polarity of the signal, and the timer’s interrupt behavior.
Page 317 Peripheral Timers Table 9-4. Timer Signal Use (Cont’d) TMxCTL PWM_OUT Mode WIDTH_CAP Mode EXT_CLK Mode Register Settings OVF_ERR Set if Initialized with: Set if the Counter wraps Unused (IRQ also set) Period < Width or (Error Condition) Period == Width or Period == 0 If PERIOD_CNT: If PERIOD_CNT:...
Page 318 Operation bility (independent of the value set with the bit) and does not start PRDCNT to count when any of the following conditions are true: • Width is equal to zero • Period value is lower than width value • Width is equal to period DATA BUS TIMERx_PERIOD TIMERx_WIDTH...
Page 319 Peripheral Timers On invalid conditions, the timer sets both the and the TIMxOVF TIMIRQx bits and the Count register is not altered. Note that after reset, the timer registers are all zero. The PWM_OUT timing is shown in Figure 9-3. As mentioned earlier, 2 x is the period of the PWM waveform and TMxPRD...
Page 320 Operation PWM Waveform Generation If the bit is set, the internally-clocked timer generates rectangular PRDCNT signals with well-defined period and duty cycles. This mode also generates periodic interrupts for real-time processing. The 32-bit period ( ) and width ( ) registers are programmed TMxPRD TMxW with the values of the timer count period and pulse width modulated out-...
Page 321 Peripheral Timers Maximum period = 2 × (2 – 1) × 7.5 ns = 32 seconds.  If your application requires a more sophisticated PWM output generator, refer to Chapter 10, Pulse Width Modulation. Single-Pulse Generation If the bit is cleared, the mode generates a single pulse on PRDCNT PWM_OUT...
Page 322 Operation PERIOD 1 PULSE = 1 TMR0 ACTIVE HIGH PULSE = 1 TMR1 ACTIVE HIGH PULSE = 1 TMR2 ACTIVE HIGH TIMER ENABLE Figure 9-4. Timers with Pulses Aligned to Asserting Edge Pulse Width Count and Capture Mode (WDTH_CAP) To enable WDTH_CAP mode, set the bits in the regis- TIMODE1–0...
Page 323 Peripheral Timers DATA BUS TIMERx_PERIOD TIMERx_WIDTH RESET PCLK TIMERx_COUNTER PULSE TiMERx_I LEADING EDGE DETECT TIMER_ENABLE TOVF_ERR PERIOD_CNT INTERRUPT LOGIC INTERRUPT Figure 9-5. Timer Flow Diagram – WDTH_CAP Mode When the timer detects a first leading edge, it starts incrementing. When it detects the trailing edge of a waveform, the timer captures the current ÷...
Page 324 Operation trailing edge of the signal, the bit in the register is TIMERx_I PULSE TMxCTL set or cleared. If the bit is cleared, the measurement is initiated by a PULSE falling edge, the count register is captured to the register on the ris- WIDTH ing edge, and the period register is captured on the next falling edge.
Page 325 Peripheral Timers PCLK TIMERx_I synchronized cycle W - 1 W + 1 P - 2 P - 1 COUNTER W_BUF cycle P_BUF cycle PERIOD cycle WIDTH cycle Figure 9-6. WDTH_CAP Timing (Period Count = 1) External Event Watchdog Mode (EXT_CLK) Figure 9-7 shows a flow diagram for EXT_CLK mode.
Page 326 Operation After the timer is enabled, it waits for the first rising edge on the TIMERx_I signal. The rising edge forces the count register to be loaded by the value (0xFFFF FFFF – ). Every subsequent rising edge increments the TMxPRD count register.
Page 327 Peripheral Timers TIMERx_I PERIOD cycle P_BUF cycle P - 1 P - 2 P - 1 P - 2 COUNTER sync delay Figure 9-8. EXT_CLK Timing Interrupts This section describes all relevant registers and hardware to raise and ser- vice interrupts. Sources Each timer generates a unique interrupt request signal.
Page 328 Interrupts TMR0_ISR: bit set ustat2 TIM0IRQ; /* W1C the Timer0 bit */ dm(TM0STAT)=ustat2; instructions; instructions; instructions; RTI; TMR0_ISR.end:  Interrupt and overflow bits may be cleared simultaneously with timer enable or disable. To enable a timer’s interrupt, set the bit in the timer’s configuration IRQEN ) register and unmask the timer’s interrupt by setting the corre- TMxCTL...
Page 329 Peripheral Timers Effect Latency The timer starts 3 cycles after the bit is set. PCLK TIMEN When the timer is enabled, the count register is loaded according to the operation mode specified in the register. When the timer is dis- TMxCTL abled, the counter registers retain their state;...
Page 330 Programming Model Loopback Routing The timer support an internal loopback mode by using the SRU. more information, see “Loop Back Routing” on page 5-30. Programming Model The section describes which sequences ofsoftware steps are required to get the peripheral working successfully. PWM Out Mode Use the following procedure to configure and run the timer in PWM out mode.
Page 331 Peripheral Timers The timer produces PWM waveform with a period of 2 x period and a width of 2 x width. • When 2 x width expires, the counter is loaded with 2x(period – width) and continues counting. • When 2 x period expires, the counter is loaded with 2 x width value again and the cycle repeats.
Page 332 Programming Model 3. Valid period and width values are set in their respective registers when is set. The period and width values are measured with respect to PCLK This makes this mode coherent with the PWM_OUT mode, where the output waveforms have a period of 2 x period and a width of 2 x width.
Page 333 Peripheral Timers When the period expires, (if enabled) is set and TMR_IRQ asserted. An external clock can trigger the Timer to issue an inter- rupt and wake up an idle processor. Reads of the count register are not supported in EXT_CLK mode. Programming Examples This section provides two programming examples written for the ADSP-2136x processor processors.
Page 334 Programming Examples R0 = 0xff; dm(TM0PRD) = R0; /* Timer 0 period = 255 */ /* An interrupt is generated when the Timer senses end of the selected period */ R0 = TIM0EN; /* Enable timer 0 */ dm(TMSTAT) = R0; _main.end: jump (pc,0);...
Page 335 Peripheral Timers SRU(TIMER0_O, TIMER1_I); ustat3 = TIMODEW| /* Width Capture mode */ PULSE| /* Positive edge is active */ IRQEN| /* Enable Timer 1 Interrupt */ PRDCNT; /* Count to end of period */ dm(TM1CTL) = ustat3; R0 = TIM1EN; /* enable timer 1 */ dm(TMSTAT) = R0;...
Page 336 Programming Examples 9-28 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 337 10 PULSE WIDTH MODULATION Pulse width modulation (PWM) is a technique for controlling analog cir- cuits with a microprocessor’s digital outputs. PWM is employed in a wide variety of applications, ranging from measurement to communications to power control and conversion. Features Table 10-1 provides a brief summary of the features of this interface.
Page 338 Features Table 10-1. PWM Feature Summary (Cont’d) Feature Availability Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Interrupt Source Core Boot Capable Local Memory Clock Operation PCLK • Four independent PWM units • Center aligned PWM •...
Page 339 Pulse Width Modulation pendent signals in non-paired mode. A block diagram of the module appears in Figure 10-1. PWMx_AL PWMx_AH OUTPUT 2-PHASE PCLK DEAD CONTROL TIMING TIME PWMx_BL UNIT UNIT UNIT PWMx_BH Sync Reset Sync SYNC INTERRUPT INTERRUPT UNIT UNIT Sync RESET Figure 10-1.
Page 340 Pin Descriptions Pin Descriptions The PWM module has four groups of four PWM outputs each, for a total of 16 PWM outputs. These outputs are described in Table 10-2. Table 10-2. PWM Pin Descriptions Multiplexed Pin Direction Description Name PWM_AH3–0 PWM output of pair A produce high side drive signals.
Page 341 Pulse Width Modulation between the high and low side drive signals of each PWM chan- PWMDT0–3 nel. This ensures the correct dead time occurs at the power inverter. In many applications, there is a need to provide an isolation barrier in the gate drive circuits that turn on the power devices of the inverter.
Page 342 Operation Modes • PWM channel A and B low side duty control registers. In non-paired mode, the registers are used to PWMAL3–0 PWMBL3–0 program the low side duty cycle of the two-pairs of PWM output signals. These can be different on the high side cycles. •...
Page 343 Pulse Width Modulation asserted, the 4 PWM outputs are automatically synced to the initially pro- grammed period. In most cases, all bits can be initialized to zero, SYNC enabling the bits of the four PWM groups at the same time syn- PWM_ENx chronizes the four groups.
Page 344 Operation Modes PWM TIME DECREMENTS FROM PWM TI ME INCREMENTS FROM PWMPERIOD/2 TO PWMPERIOD/2 PWMPERIOD/2 TO PWMPERIOD/2 PWMPERIOD/2 PWMPERIOD/2 PCLK PWMPHASE BIT Figure 10-2. Operation of Internal PWM Timer Edge-Aligned Mode In edge-aligned mode, shown in Figure 10-3, the PWM waveform is left-justified in the period window.
Page 345 Pulse Width Modulation PERIOD/2 DUTY PERIOD Figure 10-3. Edge Aligned PWM Wave with High Polarity To generate constant logic high on PWM output, program the duty regis- ter with the value ≥ + period/2. To generate constant logic low on PWM output, program the duty regis- ter with the value ≥...
Page 346 Operation Modes Center-Aligned Double-Update Mode. Duty cycle values are programma- ble only twice per PWM period. This second updating of the PWM registers is implemented at the mid-point of the PWM period, producing asymmetrical PWM patterns that produce lower harmonic distortion in two-phase PWM inverters.
Page 347 Pulse Width Modulation The global status register shows the period completion status of each group. On period completion, the corresponding bit in the reg- PWMGSTAT ister is set and remains sticky. The program first reads the global status register and clears all the intended bits by explicitly writing 1. Switching Frequencies The 16-bit read/write PWM period registers, , control the...
Page 348 Operation Modes The largest value that can be written to the 16-bit register is PWMPERIODx 0xFFFF = 65,535 which corresponds to a minimum PWM switching fre- quency of: × 100 10 ----------------------- - f PWM 763Hz ) min × 2 65535 ...
Page 349 Pulse Width Modulation a maximum programmed dead time of: 9 – × × × × × Td, max 1023 2 1023 20.5micro sec PCLK This equates to an rate of 100 MHz. Note that dead time can be pro- PCLK grammed to zero by writing 0 to the registers (see “PWM Dead...
Page 350 Operation Modes mode. All illustrated time values indicate the integer value in the associ- ated register and can be converted to time by simply multiplying by the fundamental time increment, ( ) and comparing this to the two’s-com- PCLK plement counter. Note that the switching patterns are perfectly symmetrical about the midpoint of the switching period in single-update mode since the same values of the , and...
Page 351 Pulse Width Modulation The resulting on-times (active low) of the PWM signals over the full PWM period (two half periods) produced by the PWM timing unit and illustrated in Figure 10-5 on page 10-16 may be written as: The range of T ×...
Page 352 Operation Modes ond half of the PWM period. The same value for any or all of these quantities can be used in both halves of the PWM cycle. However, there is no guarantee that a symmetrical PWM signal will be produced by the tim- ing unit in this double-update mode .
Page 353 Pulse Width Modulation PWMPERIOD PWMPERIOD   – – × ---------------------------------------- ---------------------------------------- PWMCHA PWMCHA PWMDT PWMDT   PCLK PWMPERIOD PWMPERIOD   – – × ---------------------------------------- ---------------------------------------- PWMCHA – – T AL PWMCHA 2 PWMDT 1 PWMDT 2 t PCLK ...
Page 354 Operation Modes Over-Modulation The PWM timing unit is capable of producing PWM signals with variable duty cycle values at the PWM output pins. At the extreme side of the modulation process, settings of 0% and 100% modulation are possible. These two modes are termed full OFF and full ON respectively. Settings that fall between the extremes are considered normal modulation.
Page 355 Pulse Width Modulation 2 x PWMDT x PCLK from the rising edge of the opposite output. After this delay, the PWM signal is allowed to turn on, provided the desired output is still scheduled to be in the on state after the emergency dead time delay.
Page 356 Configuring Polarity Update Modes Update modes determine the frequency with which the wave forms are sampled. Single-Update In this mode, duty cycle values are programmable only once per PWM period, so that the resultant PWM patterns are symmetrical at the mid-point of the PWM period.
Page 357 Pulse Width Modulation Accuracy The PWM has 16-bit resolution but accuracy is dependent on the PWM period. In single-update mode, the same values of are used PWMA PWMB to define the on times in both half cycles of the PWM period. As a result, the effective accuracy of the PWM generation process is 2 x (or 20 ns PCLK...
Page 358 Accuracy Duty Cycle registers directly control the duty cycles of the two PWMAx PWMBx pairs of PWM output signals on the pins when not in PWM_Ax PWM_Bx switch reluctance mode. • The two’s-complement integer value in the registers controls PWMAx the duty cycle of the signals on the pins.
Page 359 Pulse Width Modulation cycle. In double update mode, the register can also be updated at PWMSEG the mid-point of the PWM cycle.  After reset, all four enable bits of the register are cleared so PWMSEG that all PWM outputs are enabled by default. Crossover Mode registers contain two bits ( ), one...
Page 360 Interrupts Interrupts For interrupt execution, the specific bit in the corresponding PWM_IRQEN register must be set including the registers based PWMCTLx IMASK LIRPTL on the programmable interrupt to be used. Whenever a period starts, the PWM interrupt is generated. Since all four PWM units share the same interrupt vector, the interrupt service routine should read the register in order to determine the source of the...
Page 361 Pulse Width Modulation call PWM_setup; call PWM_enable; nop; finish: jump finish; /* enable interrupts */ Int_enable: LIRPTL = 0; bit set MODE1 IRPTEN; /* Global interrupt enable */ bit set LIRPTL P13IMSK; /* Enable PWM default interrupt location 13 */ Int_enable.end: rts;...
Page 362 Programming Example /* 3. Configure Dead Time */ ustat3=0x0; /* PWM Dead Time Register (unsigned integer) */ dm(PWMDT0)=ustat3; /* 4. Configure Polarity (this can be changed on the fly after the PWM port is enabled) */ ustat3=0; /* PWM Polarity Select Register */ bit set ustat3 PWM_POL1AL | PWM_POL1AH;...
Page 363 Pulse Width Modulation PWMs globally. The write to PWMGCTL will kick off the transfer */ PWM_enable.end: rts; ADSP-2136x SHARC Processor Hardware Reference 10-27 www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 364 Programming Example 10-28 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 365 11 SONY/PHILIPS DIGITAL INTERFACE The Sony/Philips Digital Interface (S/PDIF) is a standard audio data transfer format that allows the transfer of digital audio signals from one device to another without having to convert them to an analog signal. Its primary features are listed in Table 11-1.
Page 366 Features Table 11-1. S/PDIF Feature Summary (Cont’d) Feature Transmitter Receiver DMA Chaining Interrupt Source Core/(DAI) Core (DAI) Boot Capable Local Memory Clock Operation PCLK/4 PCLK/4 Features The S/PDIF interface has the following additional features. • AES3-compliant S/PDIF transmitter and receiver. •...
Page 367 Sony/Philips Digital Interface Notice it is important to be familiar with serial digital application inter- face standards IEC-60958, EIAJ CP-340, AES3 and AES11. S/PDIF Transmitter The following sections provide information on the S/PDIF transmitter. Pin Descriptions Table 11-2 provides descriptions of the pins used for the S/PDIF transmitter.
Page 368 S/PDIF Transmitter Table 11-2. S/PDIF Transmitter Pin Descriptions (Cont’d) Internal Node Description DIT_O Output Transmit biphase mark encoded data stream. DIT_BLKSTART_O Output Transmit block start. Indicates the last frame of the current block. This is high for the entire duration of the last frame.
Page 369 Sony/Philips Digital Interface Functional Description The S/PDIF transmitter, shown in Figure 11-1 resides within the DAI, and it’s inputs and outputs can be routed via the SRU. It receives audio data in serial format, encloses the specified user status information, and converts it into the biphase encoded signal.
Page 370 S/PDIF Transmitter DIT_FS_I BLK_START_O TX_ENABLE DIT_DAT_I DIT_O SAMPLE BIT BIPHASE SAMPLE U, V, CS LEFT ENCODER U, V, CS BITS U, V, CS RIGHT EXT_SYNC DIT_CLK_I M_COUNT DIT_HFCLK_I BIPHASE CLOCK FREQMULT GENERATOR Figure 11-2. AES3 Output Block In addition to encoding the audio data in the bi-phase format, the trans- mitter also provides a way to easily add the channel status information to the outgoing bi-phase stream.
Page 371 Sony/Philips Digital Interface Input Data Format Figure 11-3 through Figure 11-7 shows the format of data that is sent to the S/PDIF transmitter using a variety of interfaces. Bits 31–8: 24-Bit Audio Data BITS 3–0 Validity Bit User Data Channel Status Block Start Padding (zero) Figure 11-3.
Page 372 S/PDIF Transmitter Bits 27–10: 18-Bit Audio Data BITS 5–0 Validity Bit User Data Channel Status Block Start Padding (zero) Figure 11-6. Data Packing for Right-Justified Format, 18 Bits Bits 27–12: 16-Bit Audio Data 11 10 BITS 7–0 Validity Bit User Data Channel Status Block Start Padding (zero)
Page 373 Sony/Philips Digital Interface Operation Modes The S/PDIF transmitter can operate in standalone and full serial modes. The following sections describe these modes in detail. Standalone Mode This mode is selected by setting bit 9 in the register. In this mode, DITCTL the block start bit (indicating the start of a frame) is generated internally.
Page 374 S/PDIF Receiver over sampling clock division ratio, SCDF mode select and enable, serial data input format select and validity and channel status buffer selects. By default, all the bits in this register are zero. If the channel status or validity buffer needs to be enabled (after the SRU programming is complete), first write to the buffers with the required data and then enable the buffers by setting (bit 9 of...
Page 375 Sony/Philips Digital Interface HIGH FREQUENCY CLOCK FOR DPLL (FROM ANALOG PLL) DIGITAL DCO_CLK LRCLK_REF_O (TO EXTERNAL PLL) LRCLK_FB_O (TO EXTERNAL PLL) EXTERNAL PLL PLL_CLK CLOCK DIR_CLK_O DIR_I BIPAHSE DECODING (BIPHASE STREAM) DIR_FS_O REFRAMING LOGIC DIR_DAT_O S/PDIF RECEIVER Figure 11-8. S/PDIF Receiver Block Diagram Pin Descriptions Table 11-4 provides descriptions of the pins used for the S/PDIF receiver.
Page 376 S/PDIF Receiver Table 11-4. S/PDIF Receiver Pin Descriptions (Cont’d) Internal Node Description DIR_DAT_O Output Extracted audio data output. DIR_LRCLK_FB_O Output Receiver frame sync feed back output. Input for external PLL. DIR_LRCLK_REF_O Output Receiver frame sync reference clock output. Input for external PLL. SRU Programming The SRU (signal routing unit) needs to be programmed in order to con- nect the S/PDIF receiver to the output pins or any other peripherals and...
Page 377 Sony/Philips Digital Interface Functional Description The input to the receiver ( ) is a biphase encoded signal that may DIR_I contain two audio channels (compressed or linear PCM) or non-audio data. The receiver decodes the single biphase encoded stream, producing an I S compatible serial data output that consists of a serial clock, a left-right frame sync, and data (channel A/B).
Page 378 Notice there are various performance characteristics to consider when con- figuring for analog PLL mode. For more information using PLLs, visit the Analog Devices Inc. web site at: http://www.analog.com/embedded-processing-dsp/processors Register Descriptions The ADSP-2136x processor contains four registers that are used to enable/disable S/PDIF receiver, to manage its operation, and to report sta- tus.
Page 379 Sony/Philips Digital Interface trol values, and enable the internal digital PLL by clearing the DIR_PLLDIS bit if it was cleared initially. At this point, the receiver attempts to lock. For a detailed description of this register, see “Receive Control Register (DIRCTL)”...
Page 380 S/PDIF Receiver tion. After the receiver is locked, the other status bits in the receiver status ) and the channel status ( ) registers can be read. Inter- DIRSTAT DIRCHANL/R rupts can be also used with some status bits. No Stream error. The bit (5) is asserted whenever the DIR_NOSTREAM AES3/SPDIF stream is disconnected.
Page 381 Sony/Philips Digital Interface Clock Recovery The phased-locked loop for the AES3/SPDIF receiver is intended to recover the clock that generated the AES3/SPDIF biphase encoded stream. This clock is used by the receiver to clock in the biphase encoded data stream and also to provide clocks for either the SPORTs, sample rate converter, or the AES3/SPDIF transmitter.
Page 382 Channel Decoding  Only the first 5 channel status bytes (40-bit) of a frame are stored into the S/PDIF receiver status registers. Compressed or Non-linear Audio Data The S/PDIF receiver processes compressed as well as non-linear audio data according to the supported standards. The following sections describe how this peripheral handles different data.
Page 383 Sony/Philips Digital Interface  The S/PDIF receiver supports the DTS stream. The DTS specifica- tions support frame sizes of 256, 512, 1024, 2048 and 4096. The on-chip S/PDIF receiver supports the 256, 512 and 1024 DTS frames. The DTS test kit frames with 2048 and 4096 frame sizes can be detected by adding the sync detection logic in software by using a software counter to check for the DTS header every 2048 and 4096 frames respectively.
Page 384 Interrupts • 1000 = single channel double frequency mode–stereo left • 1001 = single channel double frequency mode–stereo right Interrupts All S/PDIF interrupts are generated by the transmitter and receiver and processed through the DAI interrupt controller which can generate an interrupt signal using the ( ) registers.
Page 385 Sony/Philips Digital Interface Notice that parity error and biphase error are ORed together to form a interrupt. DIR_ERROR_INT Whenever there is a change in channel status information, the bit in the register is set. The DIR_STATCNG_INT DAI_IRPTL_x bit is asserted high whenever the CRCC check of the DIR_CRCERROR_INT bits fail.
Page 386 Programming Model desired mode in the transmitter control register. This setup can be accom- plished in three steps. 1. Connect the transmitter’s four required input signals and one biphase encoded output in the SRU. The four input signals are the serial clock ( ), the serial frame sync ( ), the serial...
Page 387 Sony/Philips Digital Interface 2. Initialize the register to enable the data decoding. Note that DIRCTL this peripheral is enabled by default. Interrupted Data Streams on the Receiver When using the S/PDIF receiver with data streams that are likely to be interrupted, (in other words unplugged and reconnected), it is necessary to take some extra steps to ensure that the S/PDIF receiver’s digital PLL will re lock to the stream.
Page 388 Programming Model /* Enable no-stream Interrupt on Falling Edge. Interrupt occurs when the stream is reconnected */ dm(DAI_IRPTL_FE) = ustat1; /* Enable Hi-priority DAI interrupt */ dm(DAI_IRPTL_PRI) = ustat1; /* If more than 1 DAI interrupt is being used, it is neces- sary to determine which interrupt occurred here */ /* Interrupt Service Routine for the DAI Hi-Priority Inter- rupt.
Page 389 12 ASYNCHRONOUS SAMPLE RATE CONVERTER The asynchronous sample rate converter (SRC) block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using any internal processor resources. Further- more, the SRC blocks can be configured to operate together to convert multichannel audio data without phase mismatches.
Page 390 Features Table 12-1. SRC Feature Summary (Cont’d) Feature Availability Transmission Half Duplex Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Interrupt Source Core (DAI) Boot Capable Local Memory Yes (RAM, ROM) Clock Operation PCLK/4 •...
Page 391 Asynchronous Sample Rate Converter • Matched Phase Mode to compensate for group delays (ADSP-21364 only) • Linear phase FIR filter • Controllable soft mute Pin Descriptions The SRC has two interfaces: an input port and an output port.Table 12-2 describes the six inputs and two outputs for the IP (input port) and OP (output port).
Page 392 Functional Description For normal operation, the data, clock, and frame sync signals need to be routed as shown in Table 12-3. Table 12-3. SRC DAI/SRU Signal Routing Internal Node DAI Connection SRU Register Inputs SRC3–0_CLK_IP_I Group A SRU_CLK2–1 SRC3–0_CLK_OP_I SRC3–0_FS_IP_I Group C SRU_FS2–1 SRC3–0_FS_OP_I...
Page 393 Asynchronous Sample Rate Converter sample rates and provides the RAM and ROM start addresses SRCx_FS_OP for the start of the FIR filter convolution.  Unlike other peripherals, the sample rate converters own local memories (RAM and ROM) which arededicated for the purpose of sample rate conversion only.
Page 394 Functional Description RIGHT DATA IN ROM A HIGH FIFO LEFT DATA IN ROM B ORDER INTERPOLATION ROM C ROM D DIGITAL SRCx_FS_IP FIR FILTER SERVO LOOP COUNTER SRCx_DAT_OP SAMPLE RATE RATIO SRCx_FS_IP SAMPLE RATE SRCx_FS_OP RATIO EXTERNAL RATIO (MATCHED PHASE MODE) Figure 12-2.
Page 395 Asynchronous Sample Rate Converter The digital-servo loop is essentially a ramp filter that provides the initial pointer to the address in RAM and ROM for the start of the FIR convolu- tion. The RAM pointer is the integer output of the ramp filter while the ROM pointer is the fractional part.
Page 396 Functional Description > . The ratio is calculated by comparing the out- SRCx_FS_IP SRCx_FS_OP put of an counter to the output of an counter. If SRCx_FS_OP SRCx_FS_IP > > , the ratio is held at one. If SRCx_FS_OP SRCx_FS_IP SRCx_FS_IP , the sample rate ratio is updated if it is different by more than SRCx_FS_OP periods from the previous...
Page 397 Asynchronous Sample Rate Converter De-Emphasis Filter signal asserts when a new frame of left and right data is SRCx_FS_IP_I available for the de-emphasis filter and the SRC. The de-emphasis filter is used to de-emphasize audio data that has been emphasized. The type of de-emphasis filter is selected by the bits and is based SRCx_DEEMPHASIS1-0...
Page 398 Functional Description Automatic Mute The mute feature of the SRC can be controlled automatically in hardware using the signal by connecting it to the signal. Note MUTE_IN MUTE_OUT that by default, the register connects the signal to the SRCMUTE MUTE_IN signal, but not vice versa.
Page 399 Asynchronous Sample Rate Converter This mode is useful for automatic detection of non-PCM audio data received from the S/PDIF receiver. Register Descriptions The SRC uses five registers to confi g ure and operate the SRC module. For complete register and bit descriptions, see “Sample Rate Converter Regis- ters”...
Page 400 Register Descriptions When the is set or there is a change in the sample rate SRCx_ENABLE between , the signal is asserted. SRCx_FS_IP_I SRCx_FS_OP_I MUTE_OUT signal remains asserted until the digital servo loop's internal MUTE_OUT fast settling mode is complete. When the digital servo loop has switched to slow settling mode, the signal is de-asserted.
Page 401 Asynchronous Sample Rate Converter Ratio Registesr (SRCRATx) registers can be read to find the ratio of output SRCRAT0 SRCRAT1 to input sampling frequency. This ratio is reported in 4.11 (integer.frac- tion) format where the 15-bit value of the normal binary number is comprised of 4 bits for the integerand 11 bits for the fraction.
Page 402 Operation Modes RIGHT CHANNEL LEFT CHANNEL LRCLK SCLK SDATA LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL LRCLK LEFT CHANNEL RIGHT CHANNEL SCLK SDATA S MODE – 16 BITS TO 24 BITS PER CHANNEL RIGHT CHANNEL LEFT CHANNEL LRCLK SCLK SDATA...
Page 403 Asynchronous Sample Rate Converter data into the 64-bit shift register. The input to the shift register is con- nected to , and the output is connected to SRCx_TDM_OP_I SRCx_DAT_OP_O By connecting the to the of the next SRC, SRCx_DAT_OP_O SRCx_TDM_OP_I a large shift register is created, which is clocked by SRCx_CLK_OP_I TDM Input Daisy Chain...
Page 404 Operation Modes TDM IP Daisy Chain Clock, FS MASTER SRC2_DAT_IP_I SRC1_DAT_IP_I SRC0_DAT_IP_I SRC2_TDM_IP_O SRC1_TDM_IP_O SRC0_TDM_IP_O SPORT_Dx_O SRC2_TDM_OP_I SRC1_TDM_OP_I SRC0_TDM_OP_I SPORT_Dx_I MASTER SRC2_DAT_OP_O SRC1_DAT_OP_O SRC0_DAT_OP_O Clock, FS TDM OP Daisy Chain Figure 12-4. TDM Input/Output Modes Bypass Mode When the bit is set (=1), the input data bypasses the sample rate BYPASS converter and is sent directly to the serial output port.
Page 405 Asynchronous Sample Rate Converter between two or more adjacent sample rate converters that are operating with the same input and output clocks. When the bit is set SRCx_MPHASE (=1), the SRC, a matched phase mode slave accepts the sample rate ratio transmitted by another SRC, the matched phase mode master, through its serial output as shown in Figure...
Page 406 Operation Modes signals may be asynchronous with SRCx_FS_IP SRCx_FS_OP respect to each other in this mode. Note there must be 32 SRCx_CLK_OP cycles per subframe in matched-phase mode (24-bits data and 8-bits phase match). Data Format Matched-Phase Mode The SRC supports the matched-phase mode for all serial output data for- mats;...
Page 407 Asynchronous Sample Rate Converter ≥ ------------------------------ - ------------------------------ - onds for SRCx_FS_OP SRCx_FS_IP SRCx_FS_IP SRCx_FS_IP SRCx_FS_IP     × ≤ ------------------------------ - -------------------------------- - ------------------------------ - onds for SRCx_FS_OP SRCx_FS_IP     SRCx_FS_IP SRCx_FS_OP SRCx_FS_IP Interrupts The SRC mute-out signal can be used to generate interrupts on their ris- ing edge, falling edge, or both, depending on how the DAI interrupt mask registers (...
Page 408 Interrupts 12-20 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 409 13 PRECISION CLOCK GENERATOR The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A and B, are id entical in functionality and operate independently of each other.
Page 410 Functional Description Table 13-1. PCG Port Feature Summary (Cont’d) Feature PCGA–B Transmission Full Duplex Access Type Data Buffer Core Data Access DMA Data Access DMA Channels DMA Chaining Interrupt Source Boot Capable Local Memory Clock Operation CLKIN Functional Description The unit that generates the bit clock is relativelysimple, since digital clock signals are usually regular and symmetrical.
Page 411 Precision Clock Generator pin or from any of the (DAI pins). This allows a design CLKIN PCG_EXTx_I to contain an external clock with performance specifications appropriate for the application target. PRECISION CLOCK GENERATOR PCG_SYNC_CLKx_I external sync CLKIN PCG_CLKAB_O DIVIDER >1 CLOCK external sync PCG_FSAB_O...
Page 412 Functional Description  Any clock or frame sync unit shouldbe disabled (have its enable bit cleared) before changing any of the associated parameters. After disabling the PCG, a delay of N core clock cycles where N = PCG source clock period ÷ period) should be provided before pro- CLKIN gramming PCG with new parameters.
Page 413 Precision Clock Generator SRU Programming To use the PCG, route the required inputs using the SRU as described in Table 13-3. Also, use the SRU to connect the outputs to the desired DAI pin. Table 13-3. PCG DAI/SRU Connections Internal Nodes DAI Group SRU Register Inputs...
Page 414 Clock Inputs • PCG_CTLx1 register. Enables the clock and frame sources, it includes the clock sync divider and the frame sync phase low pulse. • PCG_PWx register. Enables the different operation modes like normal or bypass (either direct bypass or a one shot). •...
Page 415 Precision Clock Generator more than the high period of the output clock. For higher values of an odd divisor, the duty cycle is close to 50%.  A PCG clock output cannot be fed to its own input. Frame Sync Outputs Each of the two units also produces a synchronization signal for framing serial data.
Page 416 Frame Sync Outputs The phase of the frame sync output is determined by the value of the phase control. If the phase is zero, then the positive edges of the clock and frame sync coincide, provided the divisors of the clock and frame sync are the same, the source for the clock and frame sync is also the same, and if clock and frame sync are enabled at the same time using a single instruction.
Page 417 Precision Clock Generator External Trigger Mode The frame sync output may be synchronized with an external signal by programming the register (shown in Figure A-34 on page A-69) PCG_SYNC and the PCG control registers ( ) appropri- PCG_CTLA0–1 PCG_CTLB0–1 ately. In this mode, the rising edge of the external signal starts the frame sync output generation (shown in Figure 13-2).
Page 418 External Trigger Mode The clock output cannot be aligned with the rising edge of the external clock as there is no phase programmability. Once the clock units have been enabled (by programming bit 1 and bit 17 of the register) PCG_SYNC these outputs are activated when a low-to-high transition is sensed in the external clock (...
Page 419 Precision Clock Generator The frame sync divisors ( bits) are specified in bits 19–0 of the cor- FSxDIV responding PCG control registers ( ). The pulse width of the PCG_CTLx0 frame sync output is equal to the number of input clock periods specified in the 16-bit field of the PCG pulse width register ( PCG_PW Phase Shift...
Page 420 Phase Shift • Clock and frame sync are enabled at the same time using a single atomic instruction. • Frame sync divisor is an integral multiple of the clock divisor. If the phase shift is 0, the clock and frame sync outputs rise at the same time.
Page 421 Precision Clock Generator Pulse Width Pulse width is the number of input clock periods for which the frame sync output is high. Pulse width should be less than the divisor of the frame sync. The pulse width of frame sync A is specified in the bits (15–0) PWFSA of the...
Page 422 Phase Shift Bypass as a Pass Through When the bit in the register equals 0, the unit is STROBEx PCG_PWx bypassed and the output equals the input. If, for example, (bit 1) INVFSA for unit A or (bit 17) for unit B is set, then the signal is inverted INVFSB (see Figure...
Page 423 Precision Clock Generator As shown in Figure 13-5, the output pulse width is equal to the period of the SRU source signal ( for frame sync A, for frame MISCA2_I MISCA3_I sync B). The pulse begins at the second rising edge of following MISCAx_I a rising edge of the clock input.
Page 424 Programming Examples Programming Examples This section contains three programming examples: “Setup for I S or Left-Justified DAI” on page 13-16 “Channel B Clock and Frame Sync Divisors” on page 13-21 Setup for I S or Left-Justified DAI This example shows how to set up two precision clock generators using the S/PDIF receiver and an asynchronous sample rate converter (SRC) to interface to an external audio DAC.
Page 425 Precision Clock Generator Table 13-4. Precision Clock Generator Division Ratios (33.330 CLKIN) PCG Divisors Sample Rate kHz) PCG CLOCK SCLK FSYNC INPUT 130.195 65.098 43.398 32.549 1024 26.039 1280 21.699 1536 18.599 1792 1 The frame sync divisor should be an even integer in order to produce a 50% duty cycle waveform.
Page 426 Programming Examples  The combined PCGs can provide a selection of synchronous clock frequencies to support alternate sample rates for the SRCs and external DACs. However, the range of choices is limited by CLKIN and the ratio of which is normally fixed at PCG_CLKx_O:SCLK:FSYNC 256:64:1 to support digital audio, left-justified, I S, and...
Page 427 Precision Clock Generator FS OUT = 65.1 kHz 24-BIT LEFT-JUSTIFIED ADSP-21364 PLAYER SDATA OUT D AI_P8 RxSCLK D AI_P19 SDATA IN D AI_P9 RxLRCLK SPDIF LRCLK IN SPDIF IN ASRC SDATA IN DAI_P10 (FS IN , 44.1 kHz) SC LK IN FSYNC A (FS OU T ) PCG_ FSA_O...
Page 428 Programming Examples -------------------------------------------------------------- FS_B_Ph_Hi/FS_B_Div PCG_CTLB0 0x24C2 0x800/00000 FS_B_Ph_Lo/CLK_B_Div PCG_CTLB1 0x24C3 0x000/00002 PW_FS_B/PW_FS_A PCG_PW 0x24C4 0x0000:0000 **************************************************************/ #include <def21365.h> /* PCGA --> SCLK & FSYNC Divisors, Sample Rate = 65.098 kHz */ #define PCGA_CLK_DIVISOR 0x0008 /* SCLK output = 64xFs */ #define PCGA_FS_DIVISOR 0x0200 /* FSYNC output = Fs */...
Page 429 Precision Clock Generator ustat1 = dm(PCG_CTLB0); bit clr ustat1 ENFSA; dm(PCG_CTLB0) = ustat1; /* Set FSYNC_A and FSYNC_B Pulse Width to 50% Duty Cycle (default) */ r0 = 0x00000000; dm(PCG_PW) = r0; dm(PCG_SYNC) = r0; Init_PCG.end: rts; Channel B Clock and Frame Sync Divisors This section provides two programming examples written for the ADSP-2136x processor.
Page 430 Programming Examples #define PBEN_HIGH_Of 0x01 //Bit Positions #define DAI_PBO2 #define DAI_PBOE2 #define PCG_PWB /* Bit definitions */ #define ENFSB 0x40000000 #define ENCLKB 0x80000000 /* Main code section */ .global _main; .section/pm seg_pmco; _main: /* Route PCG Channel B clock to DAI Pin 1 via SRU */ /* Route PCG Channel B frame sync to DAI Pin 2 via SRU */ r0 = PCG_CLKB_P|(PCG_FSB_P<<DAI_PB02);...
Page 431 Precision Clock Generator r1 = fdep r1 by 20:10; r0 = r0 or r1; /* Phase Shift 10-19 = 0 */ dm(PCG_CTLB0) = r0; r0 = (100000); /* Clk Divisor = 100000 */ /* Use CLKIN as clock source */ /* Deposit the lower 10-bits of the Phase Shift in the */ /* correct position in PCG_CTLB0 (Bits 20-29) */ r1 = fdep r2 by 20:10;...
Page 432 Programming Examples #define PCG_CTLB0 0x24C2 #define PCG_CTLB1 0x24C3 #define PCG_PW 0x24C4 /* SRU Definitions */ #define PCG_CLKA_O 0x1c #define PCG_CLKB_P 0x39 #define PCG_FSB_P 0x3B #define PBEN_HIGH_Of 0x01 //Bit Positions #define PCG_EXTB_I #define DAI_PB02 #define PCG_PWB /* Bit Definitions */ #define ENCLKA 0x80000000 #define ENFSB 0x40000000...
Page 433 Precision Clock Generator /* Enable DAI Pins 1 & 2 as outputs */ r0 = (PBEN_HIGH_Of|(PBEN_HIGH_Of<<DAI_PBOE2)); dm(SRU_PBEN0) = r0; r0 = ENCLKA; /* Enable PCG Channel A Clock, No Channel A FS */ /* FS Divisor = 0, FS Phase 10–19 = 0 */ dm(PCG_CTLA1) = r0;...
Page 434 Programming Examples 13-26 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 435 14 SYSTEM DESIGN The ADSP-21362/3/4/5/6 processors support many system design options. The options implemented in a system are influenced by cost, per- formance, and system requirements. This chapter provides the following system design information: • “Conditioning Input Signals” on page 14-2 •...
Page 436 Conditioning Input Signals and testing of your application code and hardware can begin without debugging the JTAG port.  Before proceeding with this chapter it is recommended that you become familiar with the ADSP-2136x processor core architecture. This information is presented in the SHARC Processor Programming Reference.
Page 437 System Design teresis allowed is due to the restrictions on the tolerance of the V TTL input levels under worst-case conditions. Refer to the ADSP-21362/3/4/5/6 SHARC Processor Data Sheet for exact specifications. Clock Input Specifications and Jitter The clock input signal must be free of ringing and jitter. Clock jitter can easily be introduced into a system where more than one clock frequency exists.
Page 438 Clocking These inputs can be asserted in arbitrary phase to the processor clock, . The processor synchronizes the inputs prior to recognizing them. CLKIN The delay associated with recognition is called the synchronization delay. Any asynchronous input must be valid prior to the recognition point in a particular cycle.
Page 439 System Design Subject to the maximum VCO frequency, the PLL supports a wide range of multiplier ratios of the input clock, . To achieve this wide multi- CLKIN plication range, the processor uses a combination of programmable multipliers in the PLL feedback circuit and output configuration blocks. The power management control register ( ) governs the operation of PMCTL...
Page 440 Clocking PLL requires some time to achieve phase lock, must be valid for a CLKIN minimum time period during reset before the signal can be deas- RESET serted. For information on minimum clock setup, see the ADSP-21362/3/4/5/6 SHARC Processor Data Sheet. ...
Page 441 System Design Hardware Control On power-up, the pins are used to select ratios of 32:1, CLK_CFG[1:0] 16:1, and 6:1 which cannot be changed during runtime. After booting however, numerous other ratios (slowing or speeding up the clock) can be selected through software control. Table 14-1 describes the internal clock to frequency ratios sup-...
Page 442 Clocking Table 14-2. Selecting Core to CLKIN Ratio Typical Crystal and Clock Oscillators Inputs 12.500 16.667 25.000 33.333 40.000 50.000 Clock Ratios Core CLK (MHz) 16:1 266.66 32:1 1 For operational limits forthe core clock frequency see the ADSP-21362/3/4/5/6 SHARC Processor Data Sheet.
Page 443 System Design bits ÷ • The pins control the PLL feedback PLLM CLK_CFG[1:0] divider unit Table 14-3. VCO Encodings PLLM Bit Settings VCO Frequency INDIV = 0 INDIV = 1 0.5x N = 3–62 0.5Nx 31.5x 1 For operational limits for the VCO clock see the ADSP-21362/3/4/5/6 SHARC Proces- sor Data Sheet.
Page 444 Clocking division ratios are implemented on the fly without entering bypass mode (since the VCO frequency does not change). The reset value for the output divisor of the bit field is 1. This value PLLD can be reprogrammed in the boot kernel to take effect immediately after startup.
Page 445 System Design Power Supplies The ADSP-2136x has a separate power supply connection for the core ) and I/O (V ). For more information on power consump- DDINT DDEXT tion, voltage levels and power-up timing, see the ADSP-21362/3/4/5/6 SHARC Processor Data Sheet. Power Supply for the PLL The ADSP-2136x on-chip PLL is supplied with two separate pins for ana- log voltage (A...
Page 446 Power-Up Sequence PLL Start-Up Before the PLL can start settling, the signal should be asserted for RESET several micro-seconds under the following conditions. For PLL informa- tion, see the ADSP-21362/3/4/5/6 SHARC Processor Data Sheet. • valid and stable core voltage ( VDDINT •...
Page 447 System Design RESET PLL_RESET CLKIN CLKIN Core Reset Delay Circuit ENA_CNT CORE_RST CLKIN 12-bit Counter Count 4096 CLKIN Cycles Delayed Internal Core Processor Reset RESETOUT Figure 14-2. Chip Reset Circuit Examples for Power Management The following examples show different methods for using the power sav- ing features in the SHARC processors.
Page 448 Power-Up Sequence Examples For VCO Clock Management There are two allowable procedures to program the VCO. The first is: 1. Set the PLL multiplier and divisor value and enable the divisor by setting the bit. DIVEN 2. After one core clock cycle, place the PLL in bypass mode by setting (= 1) the bit.
Page 449 System Design r0 = 4096; /* wait for PLL to lock at new rate (requirement for VCO change) */ lcntr = r0, do pllwait until lce; pllwait: nop; ustat2 = dm(PMCTL); /* Reading the PMCTL register value returns the DIVEN bit value as zero */ bit clr ustat2 PLLBP;...
Page 450 Processor Pin Descriptions RESET Function A reset is required to place the processor into a known good state out of power-up. Table 14-4 shows the differences between a hardware reset pin de-asserted) or a software reset (setting bit 0 in the RESET SYSCTL register).
Page 451 Data Sheet. A detailed discussion of JTAG can be found in Engineer-to-Engineer Note EE-68, Analog Devices JTAG Emulation Technical Reference. This document is available on the Analog Devices Web site at www.analog.com. Pin Impedance Like previous SHARC processors, the ADSP-2136x processors contain internal series resistance equivalent to 360 Ohms on the input path of all pins.
Page 452 Pin Multiplexing Table 14-5. Multiplexing Registers and Bits (Cont’d) Registers Used Bits Used IDP_PP_CTL IDP_PP_SELECT, PDAP_SEL PPCTL PPEN FLAG3–0 Pins As described Table 14-5 and shown in Figure 14-3, The pins can FLAG3-0 multiplex around the following four interfaces. • FLAGS (input/output) •...
Page 453 System Design processor that it has data available. For more information, see Appendix B, Interrupts. output is generated by the on-chip core timer. It indicates to TMREXP other devices that the programmed time period has expired. For informa- tion on core timer, see the SHARC Processor Programming Reference. Table 14-6.
Page 454 Pin Multiplexing PPFLGS IRQxEN PINS FLG0EN TMREXPEN IRQ0 FLAG0 FLAG0 IRQ1 FLAG1 FLAG1 IRQ2 FLAG2 FLAG2 TMREXP FLAG3 FLAG3 AD11-8 (GROUP0) Figure 14-3. FLG3–0/IRQ2–0/TMREXP Pin Multiplexing Scheme Parallel Port Pin Multiplexing As described Table 14-7 and shown in Figure 14-4, the parallel port can multiplex around the following five interfaces.
Page 455 System Design • PWM channels (output) • SPI (output, slave selects) To use the muxed parallel port pins as flags ( ), set (= 1) the FLAG15-0 (bit 20) of the register and disable the parallel port by PPFLGS SYSCTL clearing (=0) the bit (bit 0) in the register.
Page 456 Pin Multiplexing Table 14-7. Parallel Port Pin Multiplexing Scheme (Cont’d) Control F unction of Type/Comment AD15–0 IDP_PDAP_EN = 0 FLAGx Input. FLAG higher priority then PWM. FLAG can move PPEN = 0 in groups of 4. PPFLGS = 1 FLAGxEN = 1 PWMxEN = x IDP_PDAP_EN = 0 PWMx...
Page 457 System Design SPI Master Slave Select There are two SPI interfaces on-chip—the primary SPI which allows con- nectivity to the pins, the parallel port and the DAI pins. The FLAG3–0 secondary SPI, (SPIB) only routes slave selects to the DAI pins (Figure 14-5).
Page 458 Pin Multiplexing Parallel Port and DAI Pin Multiplexing Scheme Note that the direction paths from the core to the parallel port FLAG15–10 and DAI pins operate in parallel. • In output mode, if the same flag is mapped to both parallel port pins and DAI pins, then the output is driven from both pins.
Page 459 System Design Table 14-8. PWM Connection on the Parallel Port (Cont’d) Control Bits Pin Multiplexing PWM Unit PWM0EN=1 AD8=AL2 PWM2 AD9=AH2 AD10=BL2 AD11=BH2 PWM1EN=1 AD12=AL3 PWM3 AD13=AH3 AD14=BL3 AD15=BH3 SRU Flag Description Table 14-9 describes how to route the general-purpose I/O flags within the SRU.
Page 460 The signal should not only offer a suitable RESET delay, but it should also have a clean monotonic edge. Analog Devices has a range of microprocessor supervisory ICs with different features. Features include one or more of the following.
Page 461 System Design A simple power-up reset circuit is shown in Figure 14-6 using the ADM809-RART reset generator. The ADM809 provides an active low signal whenever the supply voltage is below 2.63 V. At power-up, a RESET 240 ms active reset delay is generated to give the power supplies and oscil- lators time to stabilize.
Page 462 Designing for High Frequency Operation V DDEXT +3.3V 10µF V SENSE 100nF V DDEXT 100nF ADM706TAR RESET IRQ0 ADSP-2136x Vt=+1.25V IRQ1 FLAG0 RESET Figure 14-7. Reset Generator and Power Supply Monitor Designing for High Frequency Operation Because the processor must be able to operate at very high clock frequen- cies, signal integrity and noise problems must be considered for circuit board design and layout.
Page 463 System Design Other Recommendations and Suggestions • Use more than one ground plane on the PCB to reduce crosstalk. Be sure to use lots of vias between the ground planes. One V plane for each supply is sufficient. These planes should be in the center of the PCB.
Page 464 Designing for High Frequency Operation power and ground planes with vias that touch their solder pads. Sur- face-mount capacitors are recommended because of their lower series inductances (ESL) and higher series resonant frequencies. Connect the power and ground planes to the ADSP-2136x processor’s power supply pins directly with vias—do not use traces.
Page 465 System Design A 1 GHz or better sampling oscilloscope is needed to see the signals accurately. Recommended Reading The text High-Speed Digital Design: A Handbook of Black Magic is recom- mended for further reading. This book is a technical reference that covers the problems encountered in state-of-the-art, high frequency digital cir- cuit design.
Page 466 Processor Booting Processor Booting When a processor is initially powered up, its internal SRAM is undefined. Before actual program execution can begin, the application must be loaded from an external non-volatile source such as flash memory or a host processor. This process is known as bootstrap loading or booting and is automatically performed by the processor after power-up or after a soft- ware reset.
Page 467 System Design Loading the Boot Kernel Using DMA 1. At reset, the processor is hardwired (using the boot configuration pins) to load 256 x 48-bit instruction words via a DMA starting at IVT_START_ADDRESS 2. The sequencer will halt into location until an interrupt RESET occurs.
Page 468 Processor Booting Loading the Application’s Interrupt Vector Table 1. The last header is recognized by the kernel indicating that booting has nearly finished. 2. The kernel prepares a 256 x 48-word DMA starting at IVT_START_ADDRESS This overrides the kernel with the application’s IVT. However, the elfloader needs to temporarily include the RTI instruction at the peripheral interrupt address, allowing a return from the last interrupt.
Page 469 System Design Internal Memory Kernel Load The internal memory blocks of SHARC processors are based on 4 col- umns, each of which is 16-bits in I/O wi d th. The access type is defined on the address space (for example short word address space only performs a one column access).
Page 470 Processor Booting Parallel Port Booting The SHARC processors support an 8-bit boot mode through the parallel port. The processor is configured for 8-bit boot mode when the pins = 10. For a complete diagram of the parallel port, see BOOT_CFG1–0 Figure 4-1 on page 4-3.
Page 471 System Design  Unlike previous SHARCs, the 8 to 48-bit packing mode for instructions is not supported. For instructions, the DMA reads 3 x 32-bit data which results in 2 x 48-bit instructions. Also unlike previous SHARC processors, the ADSP-21362/3/4/5/6 processors do not have a boot memory select ( ) pin.
Page 472 Processor Booting change the duration cycles ( bits, see Table 14-10) in the kernel file. PPDUR After the kernel is executed, the new duration cycle settings are applied and processor booting continues. Table 14-11. Parameter Initialization for Parallel Port Boot Parameter Register Initialization Value Comment...
Page 473 System Design Master boot mode is used when the processor is booting from an SPI-compatible serial PROM, serial FLASH, or slave host processor. The specifics of booting from these devices are discussed individually. On reset, the interface starts up in master mode performing a 384 32-bit word DMA transfer.
Page 474 Processor Booting Table 14-13. Parameter Initialization Values for SPI Master Boot (Cont’d) Parameter Register Initialization Value Comment IMSPI 32-bit data transfers × CSPI 0x180 32-bit transfers Master Header Information The transfer is initiated by the transferring the necessary header informa- tion on the interface (consisting of the read opcode and the starting address of the block to be transferred, which is usually all zeros).
Page 475 System Design FLAG0 CLOCK 16-BIT ADDRESS 8-BIT INSTRUCTION ADDRESS WORD VALID EPRO M BITS DATA Figure 14-10. SPI Master Mode Booting Using Various Serial Devices Slave Boot Mode In slave boot mode, the host processor initiates the booting operation by activating the signal and asserting the signal to the active...
Page 476 Processor Booting Table 14-14. SPI Slave Boot Bit Settings (0x4D22) Setting Comment SPIEN Set (= 1) SPI enabled SPIMS Cleared (= 0) Slave device MSBF Cleared (= 0) LSB first 10, 32-bit SPI Receive shift register word length DMISO Set (= 1) MISO MISO disabled SENDZ Cleared (= 0)
Page 477 System Design the 32-bit words received into the register and the instructions that RXSPI need to be placed in internal memory is shown in the following sections. For more information about 32- and 48-bit internal memory addressing, see the “Memory” chapter in the SHARC Processor Programming Reference. As shown in Figure 14-11, two words shift into the 32-bit receive shift...
Page 478 Processor Booting 32-Bit SPI Packing Figure 14-12 shows how a 32-bit SPI host packs 48-bit instructions exe- cuted at PM addresses 0x90000 and 0x90001. The 32-bit word is shifted to internal program memory during the 256-word kernel load. The following example shows a 48-bit instruction executed: [0x90000] 0x112233445566 [0x90001] 0x7788AABBCCDD Internal...
Page 479 System Design 16-Bit SPI Packing Figure 14-13shows how a 16-bit SPI host packs 48-bit instructions at PM addresses 0x90000 and 0x90001. For 16-bit hosts, two 16-bit words are packed into the shift register to generate a 32-bit word. The 32-bit word shifts to internal program memory during the kernel load.
Page 480 Processor Booting 8-Bit SPI Packing Figure 14-14 shows how an 8-bit SPI host packs 48-bit instructions exe- cuted at PM addresses 0x90000 and 0x90001. For 8-bit hosts, four 8-bit words pack into the shift register to generate a 32-bit word. The 32-bit word shifts to internal program memory during the load of the 256-instruction word kernel.
Page 481 System Design to 384 words. Since one 32-bit word is created from four packed 8-bit words, the total number of 8-bit words transmitted is 1536. Kernel Boot Time This section and Table 14-16 describe the minimum required booting time for the kernels (provided by the tools). There are 5 timing windows which together describe the entire boot process.
Page 482 Processor Booting The complete time for booting can be estimated by adding all 5 timing windows. Loading Kernel and Loading IVT both have the same size, however the default access time (wait states) for the IVT loading can be changed in the kernel by the user. Definition of Terms Booting When a processor is initially powered up, its internal SRAM and many...
Page 483 System Design Boot Kernel The boot kernel is an executable file which schedules the entire boot pro- cess. The temporary location of the kernel resides in the processor’s Interrupt vector location (IVT). The IVT typically has a maximum size of 256 x 48 words.
Page 484 Processor Booting Elfsplitter The elfsplitter is a tool used for no boot mode. The elfsplitter converts an executable image ( file) into a non boot stream ( file). For more .dxe .ldr information on the elfsplitter, refer to the VisualDSP tools documenta- tion.
Page 485 A REGISTERS REFERENCE The ADSP-21362/3/4/5/6 processors have general-purpose and dedicated registers in each of their functional blocks. The register reference informa- tion for each functional block includes bit definitions, initialization values, and memory-mapped addresses (for I/O processor registers). Infor- mation on each type of register is available at the following locations: •...
Page 486 For convenience and consistency, Analog Devices supplies a header file that provides these bit and registers definitions. An #include file is provided with VisualDSP++ tools and can be found in the directory.
Page 487 Registers Reference Notes on Reading Register Drawings The register drawings in this appendix provide “at-a-glance” information about specific registers. They are designed to give experienced users basic information about a register and its bit settings. When using these regis- ters, the following should be noted. 1.
Page 488 I/O Processor Registers System Control Register (SYSCTL) register is used to set up system configuration selections. Bit SYSCTL settings for this register are shown in Figure A-1 and described in Table A-1. The reset value has all bits initialized to zero. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IRQ0EN...
Page 489 Registers Reference Table A-1. SYSCTL Register (Cont’d) Name Description IRQ1EN Flag1 Interrupt Mode. 0 = FLAG1 pin is a general-purpose I/O pin. Permits core writes. 1 = FLAG1 pin is allocated to interrupt request IRQ1 IRQ2EN Flag2 Interrupt Mode. 0 = FLAG2 pin is a general-purpose I/O pin. Permits core writes. 1 = FLAG2 pin is allocated to interrupt request IRQ2 Core Timer Expired.
Page 490 Power Management Control Register (PMCTL) Table A-1. SYSCTL Register (Cont’d) Name Description PWM1EN Pulse Width Modulation1 Mode Select. 0 = AD15–12 pins in parallel port mode 1 = AD15–12 pins in PWM mode PWM2EN Pulse Width Modulation2 Mode Select. 0 = AD3–0 pins in parallel port mode 1 = AD3–0 pins in PWM mode Pulse Width Modulation3 Mode Select.
Page 491 Registers Reference  When the PLL is programmed using a multiplier and a divisor, the bits should NOT be programmed in the same DIVEN PLLBP core clock cycle. For more information, see “Bypass Clock” on page 14-10 “Example for Output Divider Management” on page 14-13.
Page 492 Power Management Control Register (PMCTL) Table A-2. PMCTL Register Bit Descriptions Name Description 5–0 PLLM PLL Multiplier. Read/Write. PLLM = 0 PLL multiplier = 64 0 < PLLM < 64 PLL multiplier = PLLM Reset value = CLK_CFG1–0 00 = 000000 = 6x 01 = 100000 = 32x 10 = 010000 = 16x 11 = 000110 = 6x (Reserved)
Page 493 Registers Reference Table A-2. PMCTL Register Bit Descriptions (Cont’d) Name Description PPPDN Parallel Port Enable/Disable. Read/Write 0 = PP is in normal mode 1 = Shutdown clock to PP Reset value = 0 SPORT1 Enable/Disable. Read/Write SP1PDN 0 = SP0–1 are in normal mode 1 = Shutdown clock to SP0–1 Reset value = 0 SP2PDN...
Page 494 Peripheral Registers Peripheral Registers The registers in the following sections are used for the peripherals that are not routed through the signal routing unit (SRU). MTM DMA Control (MTMCTL Register) The memory-to-memory (MTM) DMA register ( ) allows programs MTMCTL to transfer blocks of 64-bit data from one internal memory location to another.
Page 495 Registers Reference Parallel Port Control Register (PPCTL) The parallel port control register ( ) is used to configure and enable PPCTL the parallel port interface. The bit settings are shown in Figure A-4 described in Table A-3. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PPDS PPODIS...
Page 496 Peripheral Registers Table A-3. Parallel Port Control Register (PPCTL) Name Description PPEN Parallel Port Enable. 0 = Disable parallel port Clearing this bit clears the FIFO and the parallel status information. If , or ALE cycle has already started, it completes normally before the port is disabled.
Page 497 Registers Reference Table A-3. Parallel Port Control Register (PPCTL) (Cont’d) Name Description 11–10 Parallel Port FIFO Status. These read-only bits indicate the status of the parallel port FIFO: 00 = RXPP/TXPP is empty 01 = RXPP/TXPP is partially full 11 = RXPP/TXPP is full PPBHD Parallel Port Buffer Hang Disable.
Page 498 Peripheral Registers Table A-3. Parallel Port Control Register (PPCTL) (Cont’d) Name Description PPCHS Parallel Port Chaining Status. 0 = Chain load status not active 1 = Chain load status active. Read only. 29–19 Reserved PPCHEN Parallel Port Chaining Enable. Enables DMA chaining. 0 = DMA chaining disabled 1 = DMA chaining enabled PPODIS...
Page 499 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Sign Extend Data ILPBK SMLS Internal Loopback Enable Seamless Transfer RXFLSH Receive Buffer Flush TXFLSH Transmit Buffer Flush 15 14 13 12 11 10 PACKEN TIMOD (0–1)
Page 500 Peripheral Registers Table A-4. SPICTL Register Bit Descriptions (Cont’d) Name Description Get Data. When RXSPI is full, get data or discard incoming data. 0 = Discard incoming data 1 = Get more data, overwrites the previous data ISSEN Input Slave Select Enable. When enabled as a master, can serve as an SPIDS error-detection input for the SPI in a multi-master environment.
Page 501 Registers Reference Table A-4. SPICTL Register Bit Descriptions (Cont’d) Name Description Open Drain Output Enable. Enables open drain data output enable (for MOSI and MISO). 0 = Normal 1 = Open-drain SPI Port Enable. SPIEN 0 = SPI module is disabled 1 = SPI module is enabled PACKEN Packing Enable.
Page 502 Peripheral Registers DMA Configuration Registers (SPIDMAC, SPIDMACB) These 17-bit SPI registers are used to control DMA transfers and are shown in Figure A-6 and described in Table A-5. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPICHS DMA Chain Loading Status 15 14 13 12...
Page 503 Registers Reference Table A-5. SPIDMAC, SPIDMACB Register Bit Descriptions (Cont’d) Name Description SPICHEN SPI DMA Chaining Enable. 0 = Disable 1 = Enable 6–5 Reserved FIFOFLSH DMA FIFO Clear. 0 = Disable 1 = Enable INTERR Enable Interrupt on Error. 0 = Disable 1 = Enable Receive OverFlow Error (SPIRCV = 1).
Page 504 Peripheral Registers Table A-5. SPIDMAC, SPIDMACB Register Bit Descriptions (Cont’d) Name Description SPICHS DMA Chain Loading Status. 0 = Chain idle 1 = Chain loading in progress 31–17 Reserved SPI Baud Rate Registers (SPIBAUD, SPIBAUDB) These SPI registers are 32-bit read/write registers that are used to set the bit transfer rate for a master device.
Page 505 Registers Reference 15 14 13 12 11 10 SPIF (RO) SPIFE (RO) SPI Transmit Transfer Complete Transaction incomplete MME (W1C) TXCOL (W1C) Multimaster Error Transmit Collision Error TUNF (W1C) RXS (RO) Transmission Error (Underflow) RXSPI Data Buffer Status TXS (RO) ROVF (W1C) TXSPI Data Buffer Status Reception Error (Overflow)
Page 506 Peripheral Registers SPI Port Flags Registers (SPIFLG, SPIFLGB) registers are used to enable individual SPI SPIFLG SPIFLGB slave-select lines when the SPI is enabled as a master. This 32-bit register (bits 31–12 are reserved) is ignored if the SPI is programmed as s slave. The bit settings for these registers are shown in Figure A-8 and described...
Page 507 Registers Reference Table A-8. SPIFLG, SPIFLGB Register Bit Descriptions (Cont’d) Name Description 11–8 SPIFLGx SPI Chip Select Level Control. For CPHASE=1 the SPI does not control the chip selects. These bits give SW control to toggle the individual chip selects. 0 = Chip Select High Level 1 = Chip Select Low Level Note: the status of the FLAG3–0 pins cannot be polled from the...
Page 508 Peripheral Registers 15 14 13 12 11 10 PWM_SYNCDIS3 PWM_EN0 PWM Group 3 Disable PWM Group 0 Enable PWM_SYNCEN3 PWM_DIS0 PWM Group 3 Enable PWM Group 0 Disable PWM_SYNCDIS2 PWM_EN1 PWM Group 2 Disable PWM Group 1 Enable PWM_SYNCEN2 PWM_DIS1 PWM Group 2 Enable PWM Group 1 Disable PWM_SYNCDIS1...
Page 509 Registers Reference Table A-9. PWMGSTAT Register Bit Descriptions (Cont’d) Name Function PWM_STAT3 PWM group 3 period completion status 15–4 Reserved PWM Control Register (PWMCTLx) These registers, shown in Figure A-11 and described in Table A-10, are used to set the operating modes of each PWM block. They also allow pro- grams to disable interrupts from individual groups.
Page 510 Peripheral Registers Table A-10. PWMCTLx Register Bit Descriptions (Cont’d) Name Description 4–3 Reserved PWM_IRQEN Enable PWM Interrupts. Enables interrupts. 0 = Interrupts not enabled 1 = Interrupts enabled 15–6 Reserved PWM Status Registers (PWMSTATx) These 16-bit, read-only registers, shown in Figure A-12 and described in Table...
Page 511 Registers Reference PWM Period Registers (PWMPERIODx) These 16-bit, read/write registers control the unsigned period of the four PWM groups. PWM Output Disable Registers (PWMSEGx) These 16-bit read/write registers, shown in Figure A-13 and described in Table A-12, control the output signals of the four PWM groups. 15 14 13 12 11 10 PWM_BH...
Page 512 Peripheral Registers Table A-12. PWMSEGx Register Bit Descriptions (Cont’d) Name Description PWM_BXOV B Signal Pair Crossover Enable. Enable cross over mode for the PWM_BH and PWM_BL signal pair. 0 = Disable 1 = Enable A Signal Pair Crossover Enable. Enable cross over mode for the PWM_AXOV PWM_AH and PWM_AL signal pair.
Page 513 Registers Reference Table A-13. PWMPOLx Register Bit Descriptions (Cont’d) Name Description PWM_POL1AH Write 1 to set channel A high polarity 1 PWM_POL0AH Write 1 to set channel A high polarity 0 PWM_POL1BL Write 1 to set channel B low polarity 1 PWM_POL0BL Write 1 to set channel B low polarity 0 PWM_POL1BH...
Page 514 Peripherals Routed Through the DAI PWM Debug Status Registers (PWMDBGx) These 16-bit read-only registers aid in software debug activities. Table A-14. PWMDBGx Register Bit Descriptions Name Function PWM_AL Channel A low output signal for S/W observation PWM_AH Channel A high output signal for S/W observation PWM_BL Channel B low output signal for S/W observation PWM_BH...
Page 515 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DXS_A (31–30) Data Buffer Channel A Status Active Low Frame Sync DERR_A LAFS Channel A Error Status (sticky) Late Frame Sync DXS_B (28–27) SDEN_A Data Buffer Channel B Status DMA Channel A Enable...
Page 516 Peripherals Routed Through the DAI Table A-15. SPCTLx Register Bit Descriptions (Standard Serial) Name Description SPEN_A Enable Channel A Serial Port. 0 = Serial port A channel disabled 1 = Serial port A channel enabled 2–1 DTYPE Data Type Select. Selects the data type formatting for standard serial mode transmissions.
Page 517 Registers Reference Table A-15. SPCTLx Register Bit Descriptions (Standard Serial) (Cont’d) Name Description Internal Frame Sync Select. Selects whether the serial port uses an internally generated frame sync (if set, = 1) or uses an external frame sync (if cleared, = 0). DIFS Data Independent Frame Sync Select.
Page 518 Peripherals Routed Through the DAI Table A-15. SPCTLx Register Bit Descriptions (Standard Serial) (Cont’d) Name Description FS_BOTH FS Both Enable. This bit applies when the SPORTS channels A and B are configured to transmit/receive data. If set (= 1), this bit issues frame sync only when data is present in both transmit buffers, TXSPxA and TXSPxB.
Page 519 Registers Reference Table A-15. SPCTLx Register Bit Descriptions (Standard Serial) (Cont’d) Name Description DERR_B Channel B Error Status (sticky, read-only). Indicates if the serial trans- mit operation has underflowed or a receive operation has overflowed in the channel B data buffer. The error status bit (DERR_B) are set when the SPORTx_FS signal occurs from either an external or internal source while the TXSPxB buffer is empty.
Page 520 Peripherals Routed Through the DAI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DXS_A (31–30) L_FIRST Data Buffer Channel A Status Left Channel First DERR_A LAFS Channel A Error Status (sticky) I2S or Left-Justified Mode Select DXS_B (28–27) SDEN_A...
Page 521 Registers Reference Table A-16. SPCTLx Register Bit Descriptions (I Left-Justified) (Cont’d) Name Description PACK 16-bit to 32-bit Word Packing Enable. 0 = Disable 16- to 32-bit word packing 1 = Enable 16- to 32-bit word packing MSTR Master Clock Select. 0 = Select external clock and frame sync 1 = Select internal clock and frame sync OPMODE...
Page 522 Peripherals Routed Through the DAI Table A-16. SPCTLx Register Bit Descriptions (I Left-Justified) (Cont’d) Name Description SCHEN_B Enable Channel B Serial Port DMA Chaining. 0 = Disable serial port channel B DMA chaining 1 = Enable serial port channel B DMA chaining Reserved Buffer Hang Disable.
Page 523 Registers Reference Table A-16. SPCTLx Register Bit Descriptions (I Left-Justified) (Cont’d) Name Description DERR_A Channel A Error Status (sticky, read-only). Refer to DERR_B Channel A Data Buffer Status (read-only). Refer to DXS_B 31–30 DXS_A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LMFS/LTDV RXS_A/TXS_A (31–30)
Page 524 Peripherals Routed Through the DAI Table A-17. SPCTLx Register Bit Descriptions (Multichannel) Name Description Reserved 2–1 DTYPE Data Type Select. Selects the data type formatting for standard serial mode transmissions. For Standard serial mode, selection of companding mode and MSB format are exclusive: Multichannel Data Type Formatting Right-justify, zero-fill unused MSBs...
Page 525 Registers Reference Table A-17. SPCTLx Register Bit Descriptions (Multichannel) (Cont’d) Name Description IMFS Internal Multichannel Frame Sync Select. Selects whether the serial port uses an internally generated frame sync (if set, = 1) or uses an external frame sync (if cleared, = 0). This bit only valid for the receiver (SPORT1/3/5).
Page 526 Peripherals Routed Through the DAI Table A-17. SPCTLx Register Bit Descriptions (Multichannel) (Cont’d) Name Description ROVF_B Channel B Error Status (sticky, read-only). Indicates if the serial receive operation has overflowed (SPORT1/3/5) in the channel B data buffer. TUVF_B Channel B Error Status (sticky, read-only). Indicates if the serial trans- mit operation has underflowed (SPORT0/2/4) in the channel B data buffer.
Page 527 Registers Reference SPORT Multichannel Control Registers (SPMCTLxy) In TDM mode, the SPORTs are working in defined pairs (01/23/45). register is the multichannel control register for SPORTs SPMCTLxy including the standard and chained DMA status. (x = 0, 2, and 4; y = 1, 3, and 5, shown in Figure A-18).
Page 528 Peripherals Routed Through the DAI Table A-18. SPMCTLxy Register Bit Descriptions Name Description MCEA Multichannel Mode Enable. Standard and multichannel modes only. One of two configuration bits that enable and disable multichannel mode on serial port channels. See also, OPMODE on page A-26. 0 = Disable multichannel operation 1 = Enable multichannel operation if OPMODE = 0 4–1...
Page 529 Registers Reference Table A-18. SPMCTLxy Register Bit Descriptions (Cont’d) Name Description 22–16 CHNL Current Channel Selected. Identifies the currently selected transmit channel slot (0 to 127). (Read-only, sticky) MCEB Multichannel Enable, B Channels. 0 = Disable 1 = Enable DMA Status. Defines the DMA A/B channel status for the SPORTs 27–24 DMASxy x=0, 2, 4 and y=1, 3, 5...
Page 530 Peripherals Routed Through the DAI in the register is cleared (= 0), the se rial port does not compand the MTCCSx output during the channel’s receive time slot. SPORT Receive Select Registers (MRxCSx) Each bit, 31–0, set (= 1) in one of the four registers corresponds to MRCSx an active receive channel, 127–0, on a multichannel mode serial port.
Page 531 Registers Reference Input Data Port Registers The input data port (IDP) provides an additional input path to the pro- cessor core. The IDP can be configured as 8 channels of serial data or 7 channels of serial data and a single channel of up to a 20-bit wide parallel data.
Page 532 Peripherals Routed Through the DAI Table A-19. IDP_CTL0 Register Bit Descriptions Bits Name Description 3–0 IDP_NSET Threshold Interrupt. The contents of the IDP_NSET bits represent a threshold number of entries (N) in the FIFO. When the FIFO fills to a point where it has more (N+1) than N words (data in FIFO exceeds the value set in the IDP_NSET bit field), a DAI interrupt is generated.
Page 533 Registers Reference Table A-19. IDP_CTL0 Register Bit Descriptions (Cont’d) Bits Name Description 10–8 IDP_SMODE0 Serial Input Data Format Mode Select. These eight inputs (0-7), each of which contains 3 bits, indicate the mode of the serial input 13–11 IDP_SMODE1 for each of the eight IDP channels. Input format: 16–14 IDP_SMODE2...
Page 534 Peripherals Routed Through the DAI Table A-20. IDP_CTL1 Register Bit Descriptions Name Description 7–0 IDP_ENx IDP Channel x Enable. These are the enable bits for accept- ing data from individual channels. Corresponding IDP_ENx must be set with IDP_EN bit to get data from Channel x.
Page 535 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP_PDAP_EN IDP_P17_PDAPMASK IDP_PDAP_RESET IDP_P18_PDAPMASK IDP_PDAP_CLKEDGE IDP_P19_PDAPMASK IDP_PDAP_PACKING (28–27) IDP_P20_PDAPMASK IDP_PP_SELECT 15 14 13 12 11 10 IDP_P16_PDAPMASK IDP_P01_PDAPMASK IDP_P15_PDAPMASK IDP_P02_PDAPMASK IDP_P14_PDAPMASK IDP_P03_PDAPMASK IDP_P13_PDAPMASK IDP_P04_PDAPMASK IDP_P12_PDAPMASK...
Page 536 Peripherals Routed Through the DAI Table A-21. IDP_PP_CTL Register Bit Descriptions (Cont’d) Name Description 28–27 IDP_PDAP_PACKING Packing. Selects PDAP packing mode. These bits mask parallel sub words from the 20 parallel input signals and packs them into a 32-bit word. The bit field indicates how data is packed.
Page 537 Registers Reference Input Data Port FIFO Register (IDP_FIFO) register (shown in Figure A-23 and described in IDP_FIFO Table A-22) provides information about the output of the 8-deep IDP FIFO. For more information, see “Data Buffer” on page 8-17. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Serial Input Data (31–4) 15 14 13 12...
Page 538 Peripherals Routed Through the DAI IDP Status Register (DAI_STAT0) register, shown Figure A-24 in and described in DAI_STAT0 Table A-23 is a read-only register. The state of all eight DMA channels is reflected in the register (bits 24–17 of the regis- IDP_DMAx_STAT DAI_STAT...
Page 539 Registers Reference Table A-23. DAI_STAT0 Register Bit Descriptions Name Description 7–0 SRU_PINGx_STAT Ping-pong DMA Channel Status. Indicates the status of ping-pong DMA in each respective channel (channel 7–0). 0 = DMA is not active 1 = DMA is active Sticky Overflow Channel Status. Provides overflow status 15–8 SRU_OVFx information for each channel (bit 8 for channel 0 through...
Page 540 Peripherals Routed Through the DAI IDP Status Register 1 (DAI_STAT1) Since the core does allow writes to the , the register, IDP_FIFO DAI_STAT1 described in Table A-24, stores the different read or writes indexes with a maximum of 8 entries each. Table A-24.
Page 541 Registers Reference 15 14 13 12 11 10 TIMODE (1–0) IRQEN Timer Mode Interrupt Enable PULSE PRDCNT Pulse Edge Select Period Count Figure A-25. TMxCTL Register Table A-25. TMxCTL Register Bit Descriptions Name Definition 1–0 TIMODE Timer Mode. 00 = Reset 01 = PWM_OUT mode (TIMODEPWM) 10 = WDTH_CAP mode (TIMODEW) 11 = EXT_CLK mode (TIMODEEXT)
Page 542 Peripherals Routed Through the DAI Each timer is provided with its own sticky status register bit. To TIMxEN enable or disable an individual timer, the bit is set or cleared. For TIMxEN example, writing a one to bit 8 sets the bit;...
Page 543 Registers Reference Table A-26. TMxSTAT Register Bit Descriptions (Cont’d) Name Description TIM0EN Timer 0 Disable Write one to disable timer 0 TIM1EN Timer 1 Enable Write one to enable timer 1 TIM1EN Timer 1 Disable Write one to disable timer 1 TIM2EN Timer 2 Enable Write one to enable timer 2 TIM2EN Timer 2 Disable...
Page 544 Peripherals Routed Through the DAI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRCy_HARD_MUTE SRCy_ENABLE SRCy Hard Mute Enable SRCy Enable SRCy_AUTO_MUTE SRCy_MPHASE SRCy Auto Hard Mute SRCy Matched Phase Mode Enable (from SPDIF RX) SRCy_LENOUT (29–28) SRCy_SMODEIN (20–18) SRCy Output Word Length...
Page 545 Registers Reference Table A-27. SRCCTLn Register Bit Descriptions (Cont’d) Name Description 2–4 SRCx_SMODEIN Serial Input Format. Selects the serial input format for SRC 0, 2 as follows: 000 = Default, format is left-justified 001 = I 010 = TDM 100 = 24-bit right-justified 101 = 20-bit right-justified 110 = 18-bit right-justified 111 = 16-bit right-justified...
Page 546 Peripherals Routed Through the DAI Table A-27. SRCCTLn Register Bit Descriptions (Cont’d) Name Description 12–13 SRCx_LENOUT Output Word Length Select. Selects the serial output word length on SRC 0, 2 as follows: 00 = 24 bits 01 = 20 bits 10 = 18 bits 11 = 16 bits Any word length less than 24 bits has dither added to the...
Page 547 Registers Reference Table A-27. SRCCTLn Register Bit Descriptions (Cont’d) Name Description 22–23 SRCy_DEEMPHASIS De-emphasis Filter Select. Enables de-emphasis on incoming audio data for SRC 1, 3. 00 = No de-emphasis 01 = 33 kHz 10 = 44.1 kHz 11 = 48 kHz SRCy_SOFTMUTE Soft Mute.
Page 548 Peripherals Routed Through the DAI SRC Mute Register (SRCMUTE) This read/write register connects an SRCx mute input and output when bit is cleared (=0). This allows SRCx to automatically SRC0_MUTE_ENx mute input while the SRC is initializing (0 = automatic muting and 1 = manual muting).
Page 549 Registers Reference Precision Clock Generator Registers The precision clock generator (PCG) consists of two identical units. Each of these two units (A and B) generates one clock ( ) and CLKA_O CLKB_O one frame sync ( ) output. These units can take an input FSA_O FSB_O clock signal from the...
Page 550 Peripherals Routed Through the DAI Table A-28. PCG_CTLx0 Register Bit Descriptions Name Description 19–0 FSxDIV Divisor for Frame Sync x. 29–20 FSxPHASE_HI Phase for Frame Sync x. This field represents the upper half of the 20-bit value for the channel x frame sync phase. See also FSxPHASE_LO (bits 29–20) in PCG_CTLx1 described on on page...
Page 551 Registers Reference Table A-29. PCG_CTLx1 Register Bit Descriptions (Cont’d) Name Description FSxSOURCE Frame Sync x Source. Master clock source for frame sync x. 0 = CLKIN source selected for clock x 1 = PCG_EXTA_I (SRU) selected for frame sync x CLKxSOURCE Clock x Source.
Page 552 Peripherals Routed Through the DAI Table A-30. PCG_PW Register Bit Descriptions (Bypass Mode) (Cont’d) Name Description 15–2 Reserved (in bypass mode, bits 15–2 are ignored). STROBEB One Shot Frame Sync B. Frame sync is a pulse with a dura- tion equal to one period of the MISCA3_I signal repeating at the beginning of every frame.
Page 553 Registers Reference Synchronization Register (PCG_SYNC) This register, in conjunction with the control registers, allows the frame sync output to be synchronized with an external clock. This register is shown in Figure A-34 and described in Table A-32. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FSA_SYNC CLKB_SYNC...
Page 554 Peripherals Routed Through the DAI Sony/Philips Digital Interface Registers The following sections describe the registers that are used to configure, enable, and report status information for the S/PDIF transceiver. Transmitter Registers Transmit Control Register (DITCTL) This 32-bit read/write register’s bits are shown in Figure A-35 described in Table...
Page 555 Registers Reference Table A-33. DITCTL Register Bit Descriptions Name Description DIT_EN Transmitter Enable. Enables the transmitter and resets the control registers to their defaults. 0 = Transmitter disabled 1 = Transmitter enabled Mute. Mutes the serial data output. DIT_MUTE 3–2 DIT_FREQ Frequency Multiplier.
Page 556 Peripherals Routed Through the DAI Table A-33. DITCTL Register Bit Descriptions (Cont’d) Name Description DIT_BLKSTART Block Start (read-only). Status bit that indicates block start (when bit 9, DIT_AUTO = 1). 0 = Current word is not block start 1 = Current word is block start USER_BITS_PEND This is a status bit and is high if user bit buffer has been writ- ten but not completely transmitted.
Page 557 Registers Reference Transmit Status Registers for Subframe B (DITCHANR) The S/PDIF transmitter stores a maximum of 5 bytes (40-bit) status infor- mation. Note that status byte 0 is available in the register. This DITCTL 32-bit read/write register is described in Table A-35.
Page 558 Peripherals Routed Through the DAI Table A-36. DIRCTL Register Bit Descriptions Name Description 1–0 DIR_BIPHASE Parity Biphase Error Control. 00 = No action taken 01 = Hold last valid sample 10 = Replace invalid sample with zeros 11 = Reserved 3–2 DIR_LOCK_ERR Lock Error Control.
Page 559 Registers Reference Receive Status Register (DIRSTAT) This 32-bit, read-only register is used to store the error bits. The error bits are sticky on read. Once they are set, they remain set until the register is read. This register also contains the lower byte of the 40-bit channel status information.
Page 560 Peripherals Routed Through the DAI Table A-37. DIRSTAT Register Bit Descriptions Name Description DIR_NOAUDIOL Non-Audio Subframe Mode Channel 1. Based on SMPTE 337M. 0 = Not non-audio subframe mode 1 = Non-audio subframe mode, channel 1 Non-Audio Subframe Mode Channel 2. Based on SMPTE DIR_NOAUDIOR 337M.
Page 561 Registers Reference Receive Status Registers for Subframe A (DIRCHANL) The S/PDIF receiver stores a maximum of 5 bytes (40-bit) status informa- tion. Note that status byte 0 is available in the register. This 32-bit DIRCTL read/write register is described in Table A-38.
Page 562 Peripherals Routed Through the DAI Table A-40. DAI Interrupt Registers Register Description DAI_IRPTL_H High priority interrupt latch register DAI_IRPTL_HS Shadow high priority interrupt latch register DAI_IRPTL_L Low priority interrupt latch register DAI_IRPTL_LS Shadow low priority interrupt latch register DAI_IRPTL_PRI Core interrupt priority assignment register DAI_IRPTL_RE Rising edge interrupt mask register DAI_IRPTL_FE...
Page 563 Registers Reference page A-107, provide status information for the IDP/PDAP DMA chan- nels. The register, shown in Figure A-66, allows programs DAI_PIN_PULLUP to enable/disable pull-up resistors. Digital Applications Interface Status Register (DAI_STAT) register is a read-only register. The state of all eight DMA DAI_STAT channels is reflected in the register (bits 24–17 of the...
Page 564 DAI Signal Routing Unit Registers Table A-41. DAI_STAT Register Bit Descriptions Name Description 7–0 SRU_PINGx_STAT Ping-pong DMA Status (Channel). Indicates the status of ping-pong DMA in each respective channel (channel 7–0). 0 = DMA is not active 1 = DMA is active Sticky Overflow Status (Channel).
Page 565 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPORT5_CLK_I (29–25) SPORT3_CLK_I (19–15) Serial Port 3 Clock Input Serial Port 5 Clock Input SPORT4_CLK_I (24–20) Serial Port 4 Clock Input 15 14 13 12 11 10 SPORT3_CLK_I (19–15) SPORT0_CLK_I (4–0)
Page 566 DAI Signal Routing Unit Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP0_CLK_I (con’t) (19–15) Input Data Port 0 Clock Input IDP2_CLK_I (29–25) Input Data Port 2 Clock Input IDP1_CLK_I (24–20) Input Data Port 1 Clock Input 15 14 13 12 11 10...
Page 567 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCG_SYNC_CLKA_I (29–25) SPIB_CLK_I (con’t) (19–15) Precision Clock Generator Serial Peripheral Interface Clock A Sync Input 2 Clock PCG_SYNC_CLKB_I (24–20) Precision Clock Generator Clock B Sync Input 15 14 13 12 11 10...
Page 568 DAI Signal Routing Unit Registers Table A-42. Group A Sources – Serial Clock (Cont’d) Selection Code Source Signal Description (Source Selection) 01011 (0xB) DAI_PB12_O Pin buffer 12 01100 (0xC) DAI_PB13_O Pin buffer 13 01101 (0xD) DAI_PB14_O Pin buffer 14 01110 (0xE) DAI_PB15_O Pin buffer 15 01111 (0xF)
Page 569 Registers Reference Serial Data Routing Registers (SRU_DATx, Group B) The serial data routing control registers (see Figure A-46 through Figure A-50) route serial data to the serial ports (A and B data channels) and the input data port. Each of the data inputs specified are connected to a data source based on the 6-bit values shown in Table A-43.
Page 570 DAI Signal Routing Unit Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRC2_DAT_IP_I (29–24) SRC0_DAT_IP_I (17–12) (con’t) Sample Rate Converter 2 Sample Rate Converter 0 Data Input Input Data Input Input SRC1_DAT_IP_I (23–18) Sample Rate Converter 1 Data Input Input...
Page 571 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP1_DAT_I (17–12) (con’t) IDP3_DAT_I (29–24) Input Data Port 1 Data Input Input Data Port 3 Data Input IDP2_DAT_I (23–18) Input Data Port 2 Data Input 15 14 13 12 11 10...
Page 572 DAI Signal Routing Unit Registers Table A-43. Group B Sources – Serial Data (Cont’d) Selection Code Source Signal Description (Source Selection) 000110 (0x6) DAI_PB07_O Pin buffer 7 000111 (0x7) DAI_PB08_O Pin buffer 8 001000 (0x8) DAI_PB09_O Pin buffer 9 001001 (0x9) DAI_PB10_O Pin buffer 10 001010 (0xA)
Page 573 Registers Reference Table A-43. Group B Sources – Serial Data (Cont’d) Selection Code Source Signal Description (Source Selection) 100000 (0x20) SRC0_DAT_OP_O SRC0 data out 100001 (0x21) SRC1_DAT_OP_O SRC1 data out 100010 (0x22) SRC2_DAT_OP_O SRC2 data out 100011 (0x23) SRC3_DAT_OP_O SRC3 data out 100100 (0x24) SRC0_TDM_IP_O SRC0 data out...
Page 574 DAI Signal Routing Unit Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPORT5_FS_I (29–25) SPORT3_FS_I (19–15) (con’t) Serial Port 3 FS Input Serial Port 5 FS Input SPORT4_FS_I (24–20) Serial Port 4 FS Input 15 14 13 12 11 10 SPORT3_FS_I (19–15)
Page 575 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP0_FS_I or PDAP_HOLD_I (19–15) IDP2_FS_I (29–25) (con’t) Input Data Port Channel 2 Input Data Port Channel FS Input 0 FS Input IDP1_FS_I (24–20) Input Data Port Channel 1 FS Input 15 14 13 12...
Page 576 DAI Signal Routing Unit Registers Table A-44. Group C Sources – Frame Sync Selection Code Source Signal Description (Source Selection) 00000 (0x0) DAI_PB01_O Pin buffer 1 00001 (0x1) DAI_PB02_O Pin buffer 2 00010 (0x2) DAI_PB03_O Pin buffer 3 00011 (0x3) DAI_PB04_O Pin buffer 4 00100 (0x4)
Page 577 Registers Reference Table A-44. Group C Sources – Frame Sync (Cont’d) Selection Code Source Signal Description (Source Selection) 11010 (0x1A) DIR_FS_O SPDIF RX frame sync output 11011 (0x1B) DIT_O SPDIF TX biphase encoded output 11100 (0x1C) PCG_FSA_O Precision frame sync A output 11101 (0x1D) PCG_FSB_O Precision frame sync B output...
Page 578 DAI Signal Routing Unit Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_PB07_I (20–14) (con’t) DAI_PB08_I (27–21) DAI Pin Buffer 7 Input DAI Pin Buffer 8 Input 15 14 13 12 11 10 DAI_PB07_I (20–14) DAI_PB05_I (6–0)
Page 579 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_PB20_I_INVERT DAI_PB19_I (20–14) (con’t) DAI_PB19_I_INVERT DAI Pin Buffer 19 Input DAI_PB20_I (27–21) DAI Pin Buffer 20 Input 15 14 13 12 11 10 DAI_PB19_I (20–14) DAI_PB17_I (6–0) DAI_PB18_I (13–7)
Page 580 DAI Signal Routing Unit Registers Table A-45. Group D Sources – Pin Signal Assignments (Cont’d) Selection Code Source Signal Description (Source Selection) 0001101 (0xD) DAI_PB14_O Pin buffer 14 0001110 (0xE) DAI_PB15_O Pin buffer 15 0001111 (0xF) DAI_PB16_O Pin buffer 16 0010000 (0x10) DAI_PB17_O Pin buffer 17...
Page 581 Registers Reference Table A-45. Group D Sources – Pin Signal Assignments (Cont’d) Selection Code Source Signal Description (Source Selection) 0100111 (0x27) SPORT1_FS_O SPORT 1 frame sync 0101000 (0x28) SPORT2_FS_O SPORT 2 frame sync 0101001 (0x29) SPORT3_FS_O SPORT 3 frame sync 0101010 (0x2A) SPORT4_FS_O SPORT 4 frame sync...
Page 582 DAI Signal Routing Unit Registers Table A-45. Group D Sources – Pin Signal Assignments (Cont’d) Selection Code Source Signal Description (Source Selection) 1000010 (0x42) DIR_FS_O SPDIF RX frame sync output 1000011 (0x43) DIR_CLK_O SPDIF RX clock output 1000100 (0x44) DIR_TDMCLK_O SPDIF RX TDM clock output 1000101 (0x45) DIT_O...
Page 583 Registers Reference register) is enabled, the inputs (PCG unit A) and MISCA2_I MISCA3_I (PCG unit B) are used asinput signals. Also notice if using the S/PDIF Tx block start output, it must be routed to the input for interrupt MISCB4_I operation.
Page 584 DAI Signal Routing Unit Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_INT_25_I DAI_INT_27_I DAI Interrupt 25 FLAG10_I DAI Interrupt 27 Flag 10 Input FLAG12_I Flag 12 Input DAI_INT_26_I DAI Interrupt 26 FLAG11_I Flag 11 Input 15 14 13 12...
Page 585 Registers Reference Table A-46. Group E Sources – Miscellaneous Signals (Cont’d) Selection Code Source Signal Description (Source Selection) 01001 (0x9) DAI_PB10_O Pin buffer 10 output as a source 01010 (0xA) DAI_PB11_O Pin buffer 11 output as a source 01011 (0xB) DAI_PB12_O Pin buffer 12 output as a source 01100 (0xC)
Page 586 DAI Signal Routing Unit Registers DAI Pin Buffer Enable Registers (SRU_PBENx, Group F) The pin enable control registers (see Figure A-62 through Figure A-65) activate the drive buffer for each of the 20 DAI pins. When the pins are not enabled (driven), they can be used as inputs. Each of the pin enables are connected, based on the 6-bit values in Table A-47.
Page 587 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PBEN13_I (17–12) (con’t) PBEN15_I (29–24) PBEN14_I (23–18) DAI Port 15 DAI Port 14 Pin Buffer Enable Input Pin Buffer Enable Input 15 14 13 12 11 10 PBEN11_I (5–0) PBEN13_I (17–12)
Page 588 DAI Signal Routing Unit Registers Table A-47. Group F Sources – Pin Output Enable Selection Code Source Signal Description (Source Selection) 000000 (0x0) Logic level low (0) 000001 (0x1) HIGH Logic level high (1) 000010 (0x2) MISCA0_O Miscellaneous control A0 output 000011 (0x3) MISCA1_O Miscellaneous control A1 output...
Page 589 Registers Reference Table A-47. Group F Sources – Pin Output Enable (Cont’d) Selection Code Source Signal Description (Source Selection) 011010 (0x1A) SPORT4_DA_PBEN_O SPORT 4 data channel A output enable 011011 (0x1B) SPORT4_DB_PBEN_O SPORT 4 data channel B output enable 011100 (0x1C) SPORT5_CLK_PBEN_O SPORT 5 clock as the output enable source 011101 (0x1D) SPORT5_FS_PBEN_O SPORT 5 frame sync output enable...
Page 590 DAI Signal Routing Unit Registers DAI Status Registers register, shown in Figure A-39 and described in DAI_STAT Table A-41, and the register, shown in Figure A-67 on DAI_PIN_STAT page A-107, provide status information for the IDP/PDAP DMA channels. DAI Pin Buffer Registers (DAI_PIN_PULLUP, DAI_PIN_STAT) register, shown in Figure A-67, provides DAI pin...
Page 591 Registers Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_PB17 DAI_PB20 DAI_PB18 DAI_PB19 15 14 13 12 11 10 DAI_PB16 DAI_PB01 DAI_PB15 DAI_PB02 DAI_PB14 DAI_PB03 DAI_PB13 DAI_PB04 DAI_PB12 DAI_PB05 DAI_PB11 DAI_PB06 DAI_PB10 DAI_PB07 DAI_PB09...
Page 592 Register Listing Register Listing This section list all available memory mapped IOP registers including the address and reset values. For core register listings, see the SHARC Processor Programming Reference. Register Mnemonic Address Description Reset Serial Port 0 and 1 Registers SPCTL0 0xC00 SPORT 0 Control Register...
Page 593 Registers Reference Register Mnemonic Address Description Reset IISP0A 0xC40 Internal memory DMA address Undefined IMSP0A 0xC41 Internal memory DMA access modifier Undefined CSP0A 0xC42 Contains number of DMA transfers remaining Undefined CPSP0A 0xC43 Points to next DMA parameters Undefined IISP0B 0xC44 Internal memory DMA address Undefined...
Page 594 Register Listing Register Mnemonic Address Description Reset DIV2 0x402 SPORT 2 divisor for TX/RX SCLK2 and FS2 DIV3 0x403 SPORT 3 divisor for TX/RX SCLK3 and FS3 SPMCTL23 0x404 SPORTs 2 & 3 Multichannel Control MT2CS0 0x405 SPORT 2 multichannel TX select, channels 31–0 Undefined MT2CS1 0x406...
Page 595 Registers Reference Register Mnemonic Address Description Reset IISP3A 0x448 Internal memory DMA address Undefined IMSP3A 0x449 Internal memory DMA access modifier Undefined CSP3A 0x44A Contains number of DMA transfers remaining Undefined CPSP3A 0x44B Points to next DMA parameters Undefined IISP3B 0x44C Internal memory DMA address Undefined...
Page 596 Register Listing Register Mnemonic Address Description Reset MR5CS1 0x80A SPORT 5 multichannel RX select, channels 63–32 Undefined MR5CS2 0x80B SPORT 5 multichannel RX select, channels 95–64 Undefined MR5CS3 0x80C SPORT 5 multichannel RX select, channels 127–96 Undefined MT4CCS0 0x80D SPORT 4 multichannel TX compand select, channels 31–0 Undefined MT4CCS1 0x80E...
Page 597 Registers Reference Register Mnemonic Address Description Reset TXSP4A 0x860 SPORT 4A transmit data Undefined RXSP4A 0x861 SPORT 4A receive data Undefined TXSP4B 0x862 SPORT 4B transmit data Undefined RXSP4B 0x863 SPORT 4B receive data Undefined TXSP5A 0x864 SPORT 5A transmit data Undefined RXSP5A 0x865...
Page 598 Register Listing Register Mnemonic Address Description Reset SPIBAUDB 0x2805 SPIB baud setup Undefined RXSPIB_SHADOW 0x2806 SPIB receive data shadow Undefined IISPIB 0x2880 Internal memory DMA address Undefined IMSPIB 0x2881 Internal memory DMA access modifier Undefined CSPIB 0x2882 Contains number of DMA transfers remaining Undefined CPSPIB 0x2883...
Page 599 Registers Reference Register Mnemonic Address Description Reset TM1CTL 0x1409 GP Timer 1 Control TM1CNT 0x140A GP Timer 1 Count TM1PRD 0x140B GP Timer 1 Period TM1W 0x140C GP Timer 1 Width TM2STAT 0x1410 GP Timer 2 Status TM2CTL 0x1411 GP Timer 2 Control TM2CNT 0x1412 GP Timer 2 Count...
Page 600 Register Listing Register Mnemonic Address Description Reset IDP_DMA_I7A 0x240F IDP DMA Channel 7 Index A for Ping Pong DMA IDP_DMA_I0B 0x2418 IDP DMA Channel 0 Index B for Ping Pong DMA IDP_DMA_I1B 0x2419 IDP DMA Channel 1 Index B for Ping Pong DMA IDP_DMA_I2B 0x241A IDP DMA Channel 2 Index B for Ping Pong DMA...
Page 601 Registers Reference Register Mnemonic Address Description Reset IDP_DMA_PC2 0x242A IDP DMA Channel 2 Ping Pong Count IDP_DMA_PC3 0x242B IDP DMA Channel 3 Ping Pong Count IDP_DMA_PC4 0x242C IDP DMA Channel 4 Ping Pong Count IDP_DMA_PC5 0x242D IDP DMA Channel 5 Ping Pong Count IDP_DMA_PC6 0x242E IDP DMA Channel 6 Ping Pong Count...
Page 602 Register Listing Register Mnemonic Address Description Reset SRU_EXT_MISCA 0x2470 SRU External Misc. A Control 0x3DEF 7BDE SRU_EXT_MISCB 0x2471 SRU External Misc. B Control 0x3DEF 7BDE SRU_PBEN0 0x2478 SRU Pin Enable 0 0x0E24 82CA SRU_PBEN1 0x2479 SRU Pin Enable 1 0x1348 D30F SRU_PBEN2 0x247A SRU Pin Enable 2...
Page 603 Registers Reference Register Mnemonic Address Description Reset PCG_CTLB1 0x24C3 Precision Clock B Control 1 PCG_PW 0x24C4 Precision Clock Pulse Width Control PCG_SYNC 0x24C5 Precision Clock Frame Sync Synchronization Peripheral Interrupt Priority Control Registers PICR0 0x2200 Peripheral Interrupt Priority Control 0 0x0A41 8820 PICR1 0x2201...
Page 604 Register Listing Register Mnemonic Address Description Reset PWMB1 0x3016 PWM Channel B Duty Control 1 PWMSEG1 0x3018 PWM Output Enable 1 PWMAL1 0x301A PWM Channel AL Duty Control 1 PWMBL1 0x301B PWM Channel BL Duty Control 1 PWMDBG1 0x301E PWM Debug Status 1 PWMPOL1 0x301F PWM Output Polarity Select 1...
Page 605 Registers Reference Register Mnemonic Address Description Reset PWMPOL3 0x341F PWM Output Polarity Select 3 0x00FF Memory-to-Memory DMA Registers MTMCTL 0x2C01 Memory-to-Memory DMA Control IIMTMW 0x2C10 MTM DMA Destination Index IIMTMR 0x2C11 MTM DMA Source Index IMMTMW 0x2C0E MTM DMA Destination Modify IMMTMR 0x2C0F MTM DMA Source Modify...
Page 606 Register Listing A-122 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 607 B INTERRUPTS This chapter provides a listing of the registers that are used to configure and control programmable interrupts. For information on interrupt vector tables and the core interrupt registers, see the SHARC Processor Program- ming Reference. Programmable Interrupt Control Registers The following sections provide descriptions of the programmable inter- rupts that are used in the ADSP-2136x processors.
Page 608 Programmable Interrupt Control Registers example, if peripheral x should be given high priority, the high priority priority interrupt source should be set as that peripheral (x). Table B-1. Default Programmable Interrupt Controller Routing Table Interrupt Ve ctor Programmable Default Default Function Priority Name Address...
Page 609 Interrupts Programmable Interrupt Control Register 0 (PICR0) This 32-bit read/write register, shown in Figure B-1, controls programma- ble priority interrupts 0–5 and the default sources. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P3I (19–15) P5I (29–25) SPORT1 Interrupt...
Page 610 Programmable Interrupt Control Registers Programmable Interrupt Control Register 1 (PICR1) This register, shown in Figure B-2, controls programmable peripheral interrupts 6–11 and the default sources. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P9I (19–15) P10I (24–20) Parallel Port Interrupt...
Page 611 Interrupts Programmable Interrupt Control Register 2 (PICR2) This register, shown in Figure B-3, controls programmable peripheral interrupts 12 through 17 as well as the default sources. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P17I (29–25) P15I (19–15) General-Purpose Timer1 Interrupt...
Page 612 Programmable Interrupt Control Registers ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 613 C AUDIO FRAME FORMATS This appendix introduces all the serial timing protocols used for audio inter-chip communications. These formats are listed and their availability in the various peripherals noted in Table C-1. Table C-1. Audio Format Availability Frame Format SPORTs IDP/SIP ASRC ASRC S/PDIF...
Page 614 Overview Overview The following protocols are available in the SHARC processor and are briefly described in this appendix. For complete information on the indus- try standard protocols, see the specification listings in each section. • Standard Serial Mode • Left-justified Mode (Sony format) •...
Page 615 Audio Frame Formats , in which the frame synchronization (FS) pulse indicates the start of SCLK valid data. Serial mode allows a flexible timing which can be used in unframed mode or framed mode. In framed mode the user can select between timing for early and late frame sync.
Page 616 S Mode The I S bus transmits audio data from 8–32 bits and control signals over separate lines. The data line carries two multiplexed data channels—the left channel and the right channel. In I S mode, if both channels on a SPORT are set up to transmit, then the SPORT transmits left and right S channels simultaneously.
Page 617 Audio Frame Formats device. If the transmitter is sending 32 bits per channel to a device with only 24 bits of internal precision, the receiver ignores the extra bits of pre- cision by not storing the bits past the 24th bit. Likewise, if the transmitter is sending 16 bits per channel to a receiving device with 24 bits of preci- sion, the receiver zero-fills the missing bits.
Page 618 TDM Mode Programs have control over various attributes of this mode. One attribute is the number of bits (8-to 32-bit word lengths). However, each sample of the pair that occurs on each frame sync must be the same length. TDM Mode Many applications require multiple I/O channels to implement the desired system functions (such as telephone line and acoustic interfaces).
Page 619 Audio Frame Formats FSTDM BCLKTDM INTERNAL INTERNAL INTERNAL AUXILIARY INTERNAL INTERNAL INTERNAL AUXILIARY DAC L0 DAC L1 DAC L2 DAC L0 DAC R0 DAC R1 DAC R2 DAC R0 BCLKTDM 24-BIT DATA –1 –2 –3 –4 20-BIT DATA –1 –2 –3 –4 16-BIT DATA...
Page 620 TDM Mode L/RCLK BCLK SLOT 1 SLOT 2 SLOT 3 BLANK SLOT SLOT 4 SLOT 5 SLOT 6 BLANK SLOT DATA LEFT 0 LEFT 1 LEFT 2 4 SCLK RIGHT 0 RIGHT 1 RIGHT 2 4 SCLK BCLK 20-BIT DATA –1 –2 –3...
Page 621 Audio Frame Formats LRCLKx (1 PERIOD) BCLKx (64 PERIODS) SDATA_INx, SDATA_OUTx 16 BITS 16 BITS BITS BITS (4 CHANNELS) Figure C-3. Packed TDM4 Mode AES/EBU/SPDIF Formats For this section, it is important to be familiar with serial digital applica- tion interface standards IEC-60958, EIAJ CP-340, AES3 and AES11. S/PDIF data is transmitted as a stream of 32-bit data words.
Page 622 AES/EBU/SPDIF Formats • The biphase encoded AES3 stream is composed of subframes (Figure C-5 on page C-12). Subframes consist of a preamble, four auxiliary bits, a 20-bit audio word, a validity bit, a user bit, a chan- nel status bit, and a parity bit. •...
Page 623 Audio Frame Formats The user bits from the channel A and B subframes are simply strung together. For more information, please refer to the AES3 standard. CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL SUBFRAME SUBFRAME FRAME 191 FRAME 1 FRAME 0 START OF BLOCK Figure C-4.
Page 624 AES/EBU/SPDIF Formats and identifies the subframe type. The next 24 time slots carry the audio sample data, which is transmitted in a 24-bit word with the least signifi- cant bit (LSB) first. When a 20-bit coding range is sufficient, time slots 8 to 27 carry the audio sample word with the LSB in time slot 8.
Page 625 Audio Frame Formats After the audio sample word, there are four final time slots which carry: 1. Validity bit (time slot 28). The validity bit is logic 0 if the audio sample word is suitable for conversion to an analog audio signal, and logic 1 if it is not.
Page 626 AES/EBU/SPDIF Formats Channel Coding To minimize the direct-current (dc) component on the transmission line, to facilitate clock recovery from the data stream, and to make the interface insensitive to the polarity of connections, time slots 4 to 31 are encoded in bi-phase mark.
Page 627 Audio Frame Formats Preambles Preambles are specific patterns that provide synchronization and identify the subframes and blocks. To achieve synchronization within one sam- pling period and to make this process completely reliable, these patterns violate the bi-phase mark code rules, thereby avoiding the possibility of data imitating the preambles.
Page 628 AES/EBU/SPDIF Formats C-16 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...
Page 629 INDEX Numerics arbitration, bus, 2-34 audience, intended, xxxi 128-channel TDM, audio 16-bit word lengths, 7-13 bipahse encoded in S/PDIF, 11-2 32-bit word lengths, 7-14 formats, IDP, 8-bit boot mode, 14-36 formats, S/PDIF, 11-5, 11-13 8-bit boot (SPI), 14-42 S, SPORTs, 6-38 8-bit word lengths, 7-13...
Page 630 Index biphase buffer (continued) encoded audio stream, 11-11, 11-13 TCB allocation, 2-21 routing data, 11-4 buffer enable (DIT_CHANBUF) bit S/PDIF receiver data register (DIR_I), (S/PDIF), 11-10 11-13 buffer hang disable (BHD) bit, 6-55, A-34, bits See peripheral specific bits, bits by A-38, A-41 name or acronym...
Page 631 Index chained DMA, 2-3, 2-20, 2-24, 2-25 clocks and system clocking (continued) chained DMA enable (SCHEN_A and clock distribution, 14-28 SCHEN_B) bit, A-33 clock input (CLKIN) pin, 14-5 chained DMA sequences, 2-21 clock polarity (CLKPL) bit, A-16 chain pointer (CPSPI) registers, SPI, clock rising edge select (CKRE) bit, 7-37, 7-39...
Page 632 Index connections, DAI, 5-20 (continued) conventions, manual, xlii DAI_PIN_STAT register, A-106 converters, A/D and D/A, 4-10 DAI_STAT register, 8-22, A-54, A-56, core PLL, 13-2 A-79 core transmit/receive operations, 7-22 edge-related interrupts, 5-28 count (CSPx) DMA registers, interrupt controller, 5-24 5-28 count (CSPx) registers, 2-20 interrupt controller registers,...
Page 633 Index data cycle duration (PPDUR) bit, 4-8, DIVx (divisor) registers, SPORT, 6-9, A-12 6-25, A-46 data direction control (SPTRAN) bit, A-34, A-38 booting, data-independent frame sync, 6-32 chained, 2-20, 2-24, 2-25 (DIFS) mode, 6-32 chained, SPI, 2-31 data type chained, SPORTs, 2-30 and companding, 6-23...
Page 634 Index (continued) enable (continued) switching from transmit to receive mode, external cock synchronization, PCG, 7-41 13-9 TCB memory allocation, 2-20 frame sync, PCG, 13-7 TCBs and, 2-20 2-31 full duplex, SPORTs, transfers, 8-20 S mode, SPORTs, 6-39 transmit or receive operations (SPI),7-37 interrupts, memory-to-memory, Dolby, DTS audio standards (S/PDIF),...
Page 635 Index equation (continued) external Index register, 2-30, 2-31, 4-14 PWM dead time, 10-13 external word count (ECPP) register, 4-10 serial clock frequency, 6-25 serial port clock divisor, 6-25 SPI clock baud rate, A-20 FE, format extension, See serial ports, word SRAM access, parallel port, 4-22 length...
Page 636 Index frame sync active low vs. active high, 6-30 hang, buffer enable bit, 14-37 A source (FSASOURCE) bit, A-67 hang, core, 2-33, 6-14, 6-15, 6-17, 6-48, delay, SPORT (MFD), 6-45 7-22, 7-44, 8-25, A-13, A-34 early vs. late, 6-31 hang, DMA controller, 4-12, 4-14 equations, 13-13...
Page 637 Index (continued) IDP bits (continued) DMA index (IDP_DMA_Ix) register, enable (IDP_ENABLE), 8-27, 8-28, 8-20, 8-21 A-48 DMA modify (IDP_DMA_Mx) register, FIFO number of samples 8-20, 8-21 (IDP_FIFOSZ), A-55, A-80 FIFO (IDP_FIFO) register, 8-17, 8-18, FIFO samples exceed interrupt 8-23, A-53 (IDP_FIFO_GTN_INT), 8-27 FIFO memory data transfer,...
Page 638 Index IMSPI (serial peripheral interface address interrupts (continued) modify) register, 7-37, 7-39 parallel port, 4-19 IMSPx (SPORT DMA address modifier) peripheral timers, 9-20 registers, 2-6, 2-18 priority interrupt control registers INDIV (input divisor) bit, (PICR), input setup and hold time, 14-4 programmable, input signal conditioning,...
Page 639 Index I/O processor (continued) left-justified mode (continued) memory access, DMA, 2-27 PWM, 10-7, A-25 non DMA interrupts, 2-28 S/PDIF, 11-3, 11-5, 11-7, A-71 program control interrupt (PCI) bit, SPORTs, setting, A-37 2-22, 2-24, 2-27, 2-28 SRC, 12-2, 12-8, 12-12, A-61 regenerated interrupts, avoiding, 2-33 SRC timing,...
Page 640 Index master mode (continued) mode (continued) SPORTs enable, 6-34, 6-39, 6-44 right-justified (IDP), master mode operation serial mode settings (IDP), SPORTs, 6-30 single channel double frequency master out slave in (MOSIx) pin, 7-5, 7-14 (SPDIF), 11-8 master-slave interconnections, standard serial, 6-34, MCM, multichannel mode, See serial port TDM (SPORT), modes, multichannel mode...
Page 641 Index multiplexing (continued) parallel port SPORT data channel, 6-38, 6-49 address latch enable (ALE) cycle, SRU clock, 5-15 bus cycles, determining, 4-17 SRU signals, bus status (PPBS) bit, 4-24 clearing registers, 4-18 configuring, 4-11 control (PPCTL) register, 4-5, 4-11, normal frame sync, 6-31 A-11 data packing,...
Page 642 Index parallel port (continued) parallel port bits (continued) pins, 4-3, transmit/receive select (PPTRAN), 4-6, polarity, 4-24, 4-25 read cycle, registers, 4-10, A-10 active low frame sync select for frame restrictions in use, 4-13 sync (INVFSx) bits, 13-13 signals, bypass mode, 13-13 SRAM memory, clock A source (CLKASOURCE) bit,...
Page 643 Index PDAP (continued) peripheral timers registers (continued) port mask bits (IDP _Pxx_PDAPMASK), timer control (TMxCTL), 9-5, A-56 A-51 timer count (TMxCNT), 9-5, (rising or falling) clock edge timer global status and control (IDP_PDAP_CLKEDGE) bit, A-52 (TMSTAT), PDAP control (IDP_PDAP_CTL) register, timer status (TMxSTAT), A-57 A-50...
Page 644 Index PMCTL (power management control) PPDS (parallel port DMA status) bit, A-13 register, A-6, PPDUR (parallel port data cycle duration) PMCTL register use in multi p lexing, 14-18 bit, 4-8, A-12 polarity PPEN (parallel port enable) bit, 4-5, A-12 ALE in parallel port, PPI (parallel port interrupt) bit, 4-16, 4-18 IDP left-right encoding,...
Page 645 Index receive data, serial port (RXSPx) registers, 16-bit read/write duty cycle registers, 10-13 receive data, SPI (RXSPI) register, 7-20 accuracy in, 10-21 receive data buffer shadow block diagram, 10-3 (RXSPI_SHADOW) register, A-23 center-aligned paired PWM receive data (RXSPI) buffer, double-update mode, 10-16 receive overflow error (SPIOVF) bit, 7-29, channel duty control (PWMA, PWMB)
Page 646 Index RXSPI_SHADOW, RXSPIB_SHADOW single channel double frequencey mode, (SPI receive buffer shadow) registers, 11-8 A-23 single update mode (PWM), 10-20 RXSPx (serial port receive buffer) registers, slave mode booting, 14-41 RXSR (SPI receive shift) register, booting SPI, 14-38 RXS (SPI data buffer status) bit, A-21 DAI, 5-3, 5-21...
Page 647 Index S/PDIF (continued) S/PDIF bits (continued) compressed audio data, 11-18 frequency multiplier (DIT_FREQ), DTS format, 11-18 A-71 external PLL feedback point connection, lock error (DIR_LOCK), A-74 11-14, A-98 lock receiver status (DIR_LOCK), A-76 frame sync (LRCLK) input, 11-4 mute receiver (DIR_MUTE), A-74 MPEG-2 format, 11-18...
Page 648 Index S/PDIF bits (continued) (continued) frame sync output (SPDIF_PLLCLK_I), DMA, switchingfrom transmit to recei v e 11-12 mode, 7-41 left channel status for sub-frame A enabling, 7-17 (DIRCHANL), A-77 examples, programming the SPI port, receiver biphase encoded data input 7-44 (DIR_I), 11-13 examples, timing,...
Page 649 Index (continued) SPI bits (continued) switching from receive to transmit mode, packing enable (PACKEN), A-17 7-41, 7-42 receive overflow error (SPIOVF), 7-29, system, configuring and enabling bits, 7-30, 7-31 7-37, A-14 seamless transfer (SMLS), A-17 TCB, 2-31 send zero (SENDZ), A-15 throughput, SENDZ (send zeros ) bit, 7-20,...
Page 650 Index SPI registers (continued) SPORT bits (continued) status (SPISTAT), 7-17, 7-19, 7-41, internal frame sync select (IFS), A-33, 7-44, A-20 A-41 status (SPISTAT, SPISTATB), A-20 internal serial clock (ICLK), 6-25, 6-27 transmit buffer (TXSPI), 7-20, 7-34, late frame sync (LAFS), A-33, A-37 A-20 number of channels (NCH),...
Page 651 Index SPORTs SPORTs (continued) See also SPORT bits, modes, registers framed and unframed data, 6-29 128-channel TDM, framed vs. unframed data example, 6-32 active low versus active high frame syncs, frame sync and serial word length, 6-26 6-30 frame sync delay, 6-45 buffer error status, 6-16...
Page 652 Index Tx/Rx on FS falling edge, 6-19 (continued) Tx/Rx on FS rising edge, 6-19 hard mute (SRC0_HARD_MUTE), using with SRU, A-60 word length, 6-20 matched phase select SPTRAN (serial port data direction (SRC0_MPHASE), A-62 control) bit, A-34, A-38 serial input format (SRC0_SMODEIN), SRAM, 1-2, 4-2, 4-8, 4-22, 14-32, 14-48 A-61...
Page 653 Index (continued) supervisory circuits, 14-26 signal groups, defined, 5-13 support, technical or customer, xxxvi signal sources, clock, A-80 switching from receive to transmit DMA, signal sources, frame sync, A-89 7-42 signal sources, miscellaneous, A-98 switching from transmit to receive DMA, signal sources, pin signal, A-93 7-41...
Page 654 Index system design (continued) test mode (continued) parallel port, DMA external word count SPORT, 6-24, 6-54, 9-21, A-44 (ECPP) register, 14-38 system, 14-2, 14-28 parallel port, DMA internal word count throughput (ICPP) register, 14-38 IDP, parallel port DMA external address memory-to-memory port, (EMPP) register, 14-38...
Page 655 Index TMxCNT (peripheral timer word count) TXSPI (SPI transmit buffer) register, 2-9, registers, 9-5, 7-20, 7-22, 7-34 TMxCTL (peripheral timer control) TXSPx (serial port transmit buffer) registers, 9-5, A-56 registers, TMxPRD (peripheral timer period) TXSR (SPI transmit shift) register, registers, TMxSTAT (peripheral timer status) register, A-57...
Page 656 Index I-28 ADSP-2136x SHARC Processor Hardware Reference www.BDTIC.com/ADI for the ADSP-21362/3/4/5/6 Processors...

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