Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 666

Operating Modes
PCLK
PERIOD
WIDTH
W_BUF
P_BUF
COUNTER
ZERO
TIMERx_O
IRQ
Figure 16-3. PWM_OUT Timing
PWM Waveform Generation
If the bit is set, the internally-clocked timer generates rectangular
PRDCNT
signals with well-defined period and duty cycles. This mode also generates
periodic interrupts for real-time processing.
The 32-bit period (
with the values of the timer count period and pulse width modulated out-
put pulse width.
When the timer is enabled in this mode, the
deasserted state each time the pulse width expires, and the signal is
asserted again when the period expires (or when the timer is started).
16-10
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cycle
cycle
2 1
) and width (
TMxPRD
ADSP-214xx SHARC Processor Hardware Reference
P/2
W/2
cycle
0 W W - 1
) registers are programmed
TMxW
signal is pulled to a
TIMERx
X = P - W
W
2 1 0 X
X - 1
cycle
cycle