Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 657

16 PERIPHERAL TIMERS
In addition to the internal core timer, the ADSP-214xx processors contain
identical 32-bit peripheral timers that can be used to interface with exter-
nal devices. Each timer can be individually configured in three operation
modes. The timers specifications are shown in
Table 16-1. Timer Specifications
Feature
Connectivity
Multiplexed Pinout
SRU DPI Required
SRU DPI Default Routing
Interrupt Control
Protocol
Master Capable
Slave Capable
Transmission Simplex
Transmission Half Duplex
Transmission Full Duplex
Access Type
Data Buffer
Core Data Access
DMA Data Access
DMA Channels
ADSP-214xx SHARC Processor Hardware Reference
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Table 16-1.
Timer1–0
No
Yes
Yes
Yes
Yes
Yes
N/A
N/A
N/A
No
N/A
N/A
N/A
16-1