Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 406

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Data Transfer

• The number of free quadlets in the local channel buffer falls below

the threshold for receive channels or:

free quadlets <=

• A receive channel detects a broken packet (ReceiverBreak,

AsyncBreak, ControlBreak or ReceiverProtocolError).

Configuring local channel buffer memory is accomplished using the

There are two modes of DMA—Ping-pong buffering and circular

There are 31 DMA channels for the 31 logical channels. Each channel can

address up to 16k words.

The DMA address is comprised of:

• A 5-bit base configured in the MLB base register set (

data type). The 5-bit base is the same for all the channels of the

same type (for example for all synchronous RX channels

MLB_SBCR31–16

• A 14-bit offset configured using the

ister. The register holds the lower 14 bits (bits 31–18 for start

address and 15–2 for end address). Bits 17–16 and bits 1–0 are

reserved and must always be written with zero.

For example, if the internal address is 0xC0100, then 19 bits of the

address translates to address 0x40100 because the internal memory offset

for the ADSP-214xx is 0x0008 0000.

www.BDTIC.com/ADI

For more information, see "Programming Model" on

act as the base).

ADSP-214xx SHARC Processor Hardware Reference

(programmed using

for the corresponding channel

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