Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 679

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value is captured.

value is captured.

3. Valid period and width values are set in their respective registers

The period and width values are measured with respect to

This makes this mode coherent with the PWM_OUT mode, where

the output waveforms have a period of 2 x period and a width of 2

Note that the first period value will not have been measured when

the first width is measured, so it is not valid. The timer sets and

returns a period value of zero in this case. When the period expires,

the period value is placed into the period register. When

sensed, read the status and perform the appropriate "write-one" to

EXT_CLK Mode

Use the following procedure to configure and run the timer in EXT_CLK

1. Reset the

EXT_CLK operation.

This configures the

setting of the

ing edge in this mode. The period register is WO and the width

ADSP-214xx SHARC Processor Hardware Reference

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bit determines when the

is set when the period expires and the

is set when the width expires and the

bit and set the configuration mode to 11 to select

bit. Note that the timer always samples the ris-

Peripheral Timers

status bit (if enabled) is

pin as an input pin regardless of the

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