Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 540

Data Transfer
DMA Channel Priority
When more than one channel has data ready, the channels always access
the register with fixed priority, from low to high channel num-
IDP_FIFO
ber (that is, channel 0 is the highest priority and channel 7 is the lowest
priority). For the I/O processor, the eight DMA channels are considered
as a group and arbitration can rotate across groups for system balance.
more information, see "Rotating DMA Channel Arbitration" on
page 2-44.
Standard DMA
The eight DMA channels each have a set of registers for standard DMA:
an I-register, an M-register and a C-register are used.
The IDP DMA parameter registers have these functions:
• Internal index registers (
internal memory address, acting as a pointer to the next internal
memory location where data is to be written.
• Internal modify registers (
the signed increment by which the DMA controller post-modifies
the corresponding internal memory Index register after each DMA
write.
• Count registers (
of words remaining to be transferred to internal memory on the
corresponding DMA channel.
This DMA access is enabled when the
the
IDP_DMA_ENx
DMA is performed according to the parameters set in the various DMA
registers and IDP control registers. An interrupt is generated after end of
DMA transfer (when the count = 0).
11-20
www.BDTIC.com/ADI
IDP_DMA_Ix
IDP_DMA_Mx
). Count registers indicate the number
IDP_DMA_Cx
bits register are set to select a particular channel. The
ADSP-214xx SHARC Processor Hardware Reference
). Index registers provide an
). Modify registers provide
bit and
IDP_EN IDP_DMA_EN
For
bit and