Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 687

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Figure 17-2. Shift Register Timing

Parallel Data Output

allel data latch is enabled. Data in the latch appears at the output

whenever this bit is set.

The data in each flip-flop is transferred to the respective latch on a posi-

tive-going transition of the

together, the shift register is always one clock pulse ahead of the latch.

ADSP-214xx SHARC Processor Hardware Reference

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Shift Register – ADSP-2147x

input. If both clocks are connected

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