Ami Configuration; Sdram Configuration; External Memory Access Restrictions - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Programming Models

AMI Configuration

For instruction fetch, the original (logical) address is multiplied by 3/2
and this address is translated depending on the bus width and
setting.
1. Assign external bank0 to AMI in the
2. Wait at least 8
3. Enable the global

SDRAM Configuration

For instruction fetch, the original (logical) address is multiplied by 3/2
and this address is translated depending on the bus width setting (
bit).
1. Assign external bank 0 to SDRAM in the
2. Wait at least 8
3. Configure the

External Memory Access Restrictions

The following external memory restrictions should be noted when writing
programs.
1. The LW mnemonic is not applicable to external memory.
2. Conditional accesses to external memory should not be based on
any of the FLAG pin status.
3. There is one cycle latency between a multiplier status change and
an arithmetic loop abort. This extra cycle is a machine cycle and
not the instruction cycle. Therefore, if there is a pipeline stall (due
to external memory access etc.) then the latency does not apply.
3-132
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cycles (effect latency).
CCLK
bit and clear (=0) the
AMIEN
cycles (effect latency).
CCLK
and registers accordingly.
SDCTL SDRRC
ADSP-214xx SHARC Processor Hardware Reference
PKDIS
register (default).
EPCTL
bit.
PKDIS
register (default).
EPCTL
bit
X16DE