Buffering Controller For Multiple Sdrams - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

• 8 x 4-bit/page 2k words
The SDRAM's page size is used to determine the system you select. All
four systems have the same external bank size, but different page sizes.
Note that larger page sizes, allow higher performance but larger page sizes
require more complex hardware layouts.

Even if connecting SDRAMs in parallel, the SDC always considers
the cluster as one external SDRAM bank because all address and
control lines feed the parallel parts as shown in
Figure 3-9. Single Processor System With SDRAM

Buffering Controller for Multiple SDRAMs

If using multiples SDRAMs or modules, the capacitive load will exceed
the controller's output drive strength. In order to bypass this problem an
external latch can be used for decoupling by setting the
This adds a cycle of data buffering to read and write accesses. An example
single processor system is shown in
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
ADSP-2147x
RAS
C
CAS
O
N
SDWE
T
SDCKE
R
O
MS3
L
A
A[15-0]
D
A[9-0]
D
R
SDA10
E
A17
S
A18
S
SDCLK
DATA[15-0]
SDDQM
Figure
External Port
Figure
RAS
SDRAM
8M x 16x 4
CAS
WE
CKE
CS
A[14-0]
BA0
BA1
CLK
DATA[15-0]
DQM
SDBUF
3-10.
3-10.
(bit 23).
3-39