Master Serial Clock And Frame Sync Rates; Timing Control Bits - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Master Serial Clock and Frame Sync Rates

The serial clock rate (
bit field in the
DIVx
can be set using the
bit setting.
The transmitter sends the MSB of the next word in the same clock cycle as
the word select (
To transmit or receive words continuously in left-justified mode, load the
register with
FSDIV
= 7.
FSDIV

Timing Control Bits

Several bits in the
fied mode operation:
• Master Mode Clock and Frame Sync (
• Word Length (
• Channel Order (
• Word Packing (
Figure 10-6 illustrates only one possible combination of settings attainable
in the left-justified mode. In this example case,
= 0. For complete descriptions of these bits, see
L_FIRST
Registers (SPCTLx)" on page
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
value) for internal clocks can be set using a
CLKDIV
register and the frame sync rate for internal frame sync
bit field in the
FSDIV
) signal changes.
SPORTx_FS
–1. For example, for 8-bit data words set
SLEN
control register enable and configure left-justi-
SPCTLx
, 8–32 bits)
SLEN
)
L_FIRST
)
PACK
A-151.
register based on the
DIVx
)
MSTR
= 1,
OPMODE LAFS
"Serial Control
Serial Ports
MSTR
= 1, and
10-29