Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 671

PCLK
TIMERx_I
synchronized
W - 1
COUNTER
W_BUF
P_BUF
PERIOD
WIDTH
IRQ
Figure 16-6. WDTH_CAP Timing (Period Count = 1)
External Event Watchdog Mode (EXT_CLK)
Figure 16-7 shows a flow diagram for EXT_CLK mode. To enable
EXT_CLK mode, set the
register. This samples the
TMxCTL
in EXT_CLK mode, the
counter is running.
The operation of the EXT_CLK mode is as follows:
1. Program the
timer external count.
2. Set the
TIMxEN
ter and starts the countdown.
3. When the period expires, an interrupt, (
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
W W + 1 P - 2
bits in the
TIMODE1–0
TIMERx_I
register should not be read when the
TMxCNT
period register with the value of the maximum
TMxPRD
bits. This loads the period value in the count regis-
Peripheral Timers
cycle
P - 1 P 0 1
W
cycle
cycle
cycle
cycle
register to 11 in the
TMxCTL
signal as an input. Therefore,
) occurs.
TIMxIRQ
2
P
P/2
W/2
16-15