Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 898

Peripheral Registers
Table A-39. PWMSEGx Register Bit Descriptions (RW) (Cont'd)
Bit Name
2 PWM_AH
3 PWM_AL
4 BHBL_XOVR
5 AHBL_XOVR
15–6 Reserved
Polarity Select Registers (PWMPOLx)
These 16-bit registers, described in
four PWM groups which can be set to either active high or active low.
Note that bit 1 has priority over bit 0, bit 3 over bit 2 and so on. In paired
mode, it is expected to maintain polarity coherency by setting the same
polarity for both the high and low side of a PWM pair.
Table A-40. PWMPOLx Register Bit Descriptions (RW)
Bit Name
0 PWM_POL1AL
1 PWM_POL0AL
A-72
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Description
Channel A High Disable. Enables or disables the channel A
output signal.
0 = Enable
1 = Disable
Channel A Low Disable. Enables or disables the channel A
output signal.
0 = Enable
1 = Disable
Crossover Enable for BH/BL Pair.
0 = Disable
1 = Enable
Crossover Enable for AH/AL Pair.
0 = Disable
1 = Enable
Table
Description
Channel AL Polarity 1.
0 = Channel AL polarity 0
1 = Channel AL polarity 1 (default)
Channel AL Polarity 0.
0 = Channel AL polarity 0
1 = Channel AL polarity 1 (default)
ADSP-214xx SHARC Processor Hardware Reference
A-40, control the polarity of the