Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 859

DDR2 Control Register 3 (DDR2CTL3)
The register includes the programmable parameters associated
DDR2CTL3
with the DDR2 extended mode register (
Table A-14 show the DDR2 control register 3 bit definitions. All the val-
ues are defined in terms of number of clock cycles. Values written into this
register are loaded into the DDR2 extended mode register during power
up (or when
Force EMR
tialized before starting the initialization sequence.

This register's contents should not be changed while DDR2 inter-
face is active. Also, whenever this register's contents are changed,
an initialization sequence must be executed to reflect this register
contents in to the DDR2 extended mode register.
15
DDR2EXTMR1 (15–14)
Mode Register 1
DDR2OBDIS
Output Buffer Disable
DDR2DQSDIS
DQS Enable
DDR2ODT150
On Die Termination
Figure A-12. DDR2CTL3 Register
Table A-14. DDR2CTL3 Register Bit Descriptions (RW)
Bit
0
1
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bit in
DDR2CTL0
14 13 12 11 10 9 8 7
Name Description
DDR2DLLEN DLL Enable.
0 = DLL enabled
1 = DLL disabled
DDR2OPDS Output Drive Strength.
0 = Full strength
1 = Reduced strength
Registers Reference
). Figure A-12
EMR1
is set). This register should be ini-
6 5 4 3 2 1 0
and
DDR2DLLEN
DLL Enable
DDR2OPDS
Output Drive Strength
DDR2ODT75
On Die Termination
DDR2AL (5–3)
Additive Latency
A-33