Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 857

Table A-12. DDR2CTL1 Register Bit Descriptions (RW) (Cont'd)
Bit
24–22
29–25
31–30
DDR2 Control Register 2 (DDR2CTL2)
Figure A-11 and
tions. Values written into this register are loaded into the DDR2 mode
register during power up (or when
set). This register should be initialized before starting the Initialization
sequence.

This register's contents should not be changed while DDR2 inter-
face is active. Also whenever this register contents are changed a
initialization sequence must be executed to reflect this register con-
tents in to the DDR2 mode register.
ADSP-214xx SHARC Processor Hardware Reference
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Name Description
DDR2TRRD Row to Row Activation Delay.
000 = Reserved.
001 = 1 clock cycle
010 = 2 clock cycles
...
111 = 7 clock cycles
DDR2TFAW Force Activation Window. For 8 banked devices up to 4
banks open in activation window. For 4 banked devices
the settings are ignored.
00000 = Reserved
00001 = 1 clock cycle
00010 = 2 clock cycles
...
11111 = 31 clock cycles
Reserved
Table A-13 show the DDR2 control register 2 bit defini-
Registers Reference
bit in the
Force LMR
register is
DDR2CTL0
A-31