Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 566

Operating Modes
cycles per subframe in matched-phase mode (24-bits data and 8-bits phase
match).
Data Format Matched-Phase Mode
The SRC supports the matched-phase mode for all serial output data for-
mats; left-justified, I
2
left-justified, I
frame are used to transmit the matched-phase data. In right-justified
mode, the upper eight bits are used to transmit the matched-phase data.
This is shown in
AUDIO DATA LEFT CHANNEL,
24 BITS
MATCHED-PHASE
CHANNEL, 16 BITS - 24 BITS
DATA, 8 BITS
Figure 12-6. Matched-Phase Data Transmission
Group Delay
When multiple SRCs are used with the same serial input port clock and
the same serial output port clock, the hysteresis causes different group
delays (phase mismatches) between multiple SRCs. The filter group delay
of the SRC is given by the equations:
16
GDS = ------------------------------ -
SRCx_FS_IP
12-14
www.BDTIC.com/ADI
2
S, right-justified, and TDM mode. Note that in the
S, and TDM modes, the lower 8 bits of each channel sub-
Figure 12-6.
MATCHED-PHASE
DATA, 8 BITS
2
Left-Justified, I S, and TDM Mode
AUDIO DATA LEFT
Right-Justified Mode
32
+ ------------------------------ - sec
SRCx_FS_IP
ADSP-214xx SHARC Processor Hardware Reference
AUDIO DATA RIGHT
CHANNEL, 24 BITS
MATCHED-PHASE
CHANNEL, 16 BITS - 24 BITS
DATA, 8 BITS
(
onds for SRCx_FS_OP
MATCHED-PHASE
DATA, 8 BITS
AUDIO DATA RIGHT
≥ )
SRCx_FS_IP