Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 730

Interrupts
Listing 20-1. Enabling DPI UART Interrupts
bit set mode1 IRPTEN;
bit set imask P1I;
ustat1=dm(PICR0);
bit set ustat1 P1I4|P1I1|P1I0;
bit clr ustat1 P1I3|P1I2;
dm(PICR0)=ustat1;
UART
The UART receive and transmit interrupts can also be programmed
through the peripheral interrupt control registers (
rupts. (By default, these interrupts are not configured in the
register—the
PICRx
This method shown in
value of the
UART_RXI
Listing 20-2. Enabling UART Interrupts
bit set mode1 IRPTEN;
bit set imask P1I;
ustat1=dm(PICR0);
bit set ustat1 P1I4|P1I1|P1I0;
bit clr ustat1 P1I3|P1I2;
dm(PICR0)=ustat1;
The following sections provide information on all of the available inter-
rupt sources.
DMA Interrupts
With system DMA enabled, the UART uses DMA to transfer data to or
from the processor. Dedicated DMA channels are available for receive and
transmit operations. Line error handling can be configured completely
independently from the receive/transmit setup.
20-16
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/* enables global interrupts */
/* unmasks P1I interrupt */
/* route UART0_RXI 0x13 to P1I */
register has to be programmed to configure them.)
Listing 20-2 uses the
or interrupts.
UART_TXI
/* enables global interrupts */
/* unmasks P1I interrupt */
/* route UART0_RXI 0x13 to P1I */
ADSP-214xx SHARC Processor Hardware Reference
) as separate inter-
PICRx
IRPTL
register with the code
PICR