Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 198

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DDR2 DRAM Controller (ADSP-2146x)

The equation for

written with 0x60C.

Note that the

DDR2 controller is enabled. When

not supported and can produce undesirable behavior. Values for

range from 0x001 to 0x3FFF.

The DDR2 controller provides two

byte) should be connected to the DDR2 DM pins.

The meaning of this pin is significant, based on the fact that the minimum

burst length is 4 and a burst is not divisible. The

to mask the data on both edges of the

than 4 sequential writes, for example a single write need to mask the data

for the next sequential 3 writes.

write commands. Every time these signals are asserted indicates the

controller masks unwanted data writes causing performance penal-

ties. For reads, the controller simply does not latch the data from

Resetting the Controller

Like any other peripheral, the DDR2 controller can be reset by hard- or a

soft reset. Both reset modes pull the

www.BDTIC.com/ADI

) – (9 + 3) = 1548 clock cycles.

is 0x614 and the

bit must be programmed to a non-zero value if the

pins are useful for performance monitoring during

drops asynchronously and the PLL goes into bypass mode

ADSP-214xx SHARC Processor Hardware Reference

= 0, operation of the controller is

pins. Both pins (for each

signal during writes in cases less

pin asynchronously low.

pins are used

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