Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 664

Operating Modes
Table 16-4. Timer Signal Use (Cont'd)
Register PWM_OUT Mode
Settings
TMxOVF
(IRQ also set)
TMxIRQ
(If enabled)
Pulse Width Modulation Mode (PWM_OUT)
In mode, the timer supports on-the-fly updates of period and
PWM_OUT
width values of the PWM waveform. The period and width values can be
updated once every PWM waveform cycle, either within or across PWM
cycle boundaries.
To enable
PWM_OUT
figuration (
TMxCTL
an output with its polarity determined by
• If
PULSE
ated at the
• If
PULSE
erated at the
The timer is actively driven as long as the
Figure 16-2 shows a flow diagram for
becomes enabled, the timer checks the period and width values for plausi-
bility (independent of the value set with the
to count when any of the following conditions are true:
• Width is equal to zero
16-8
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Set if Initialized with:
Period < Width or
Period == Width or
Period == 0
If PERIOD_CNT:
1 = Set at end of Period
0 = Set at end of Width
mode, set the
TIMODE1–0
) register. This configures the timer's
is set (= 1), an active high width pulse waveform is gener-
signal.
TIMERx
is cleared (= 0), an active low width pulse waveform is gen-
signal.
TIMERx
ADSP-214xx SHARC Processor Hardware Reference
WIDTH_CAP Mode
Set if the Counter wraps
(Error Condition)
If PERIOD_CNT:
1 = Set at end of Period
0 = Set at end of Width
bits to 01 in the timer's con-
as follows:
PULSE
field remains 01.
TIMODE
mode. When the timer
PWM_OUT
bit) and does not start
PRDCNT
EXT_CLK Mode
Unused
Set after Period Expires
and PCLK is running
signal as
TIMERx