Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 563

TDM Input Daisy Chain
In TDM input port, several SRCs can be daisy-chained together and con-
nected to the serial input port of a SHARC processor or other processor
(Figure 12-4). The SRC IP contains a 64-bit parallel load shift register.
When the
SRCx_FS_IP_I
right data into the 64-bit shift register. The input to the shift register is
connected to
SRCx_DATA_IP_I
. By connecting the
SRCx_TDM_IP_O
of the next SRC, a large shift register is created, which is clocked by
.
SRCx_CLK_IP_I

The number of SRCs that can be daisy-chained together is limited
by the maximum frequency of
exact value. For example, if the maximum frequency of
SRCx_CLK_xx_I
number of SRCs (n) that can be connected in daisy chained fashion
is: n × 64 × fs <= X MHz.
TDM Output Daisy Chain
In TDM output port, several SRCs can be daisy-chained together and
connected to the SPORT of an ADSP-214xx or other processor
(Figure 12-4). The SRC OP contains a 64-bit parallel load shift register.
When the
SRCx_FS_OP_I
data into the 64-bit shift register. The input to the shift register is con-
nected to
SRCx_TDM_OP_I
By connecting the
a large shift register is created, which is clocked by
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Asynchronous Sample Rate Converter
pulse arrives, each SRC parallel loads its left and
, while the output is connected to
SRCx_TDM_IP_O
is X MHz, and the output sample rate is fS, then
pulse arrives, each SRC loads its left and right
, and the output is connected to
to the
SRCx_DAT_OP_O
to the
, refer datasheet for
SRCx_CLK_xx_I
of the next SRC,
SRCx_TDM_OP_I
SRCx_CLK_OP_I
SRCx_DATA_IP_I
.
SRCx_DAT_OP_O
.
12-11