Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 708

Clocking
Trip Register (WDTTRIP). Sets the number of times that the WDT can
expire before the
hardware reset is applied.
Unlock Register (WDTUNLOCK). Protects the WDT configuration
space (WDTCTL, WDTCNT, WDTCURCNT and WDTTRIP regis-
ters) against accidental writes from the processor core.
Clock Select Register (WDTCLKSEL). Selects one of the 2 clock sources
for , an external source (external clock connected to
WDTCLK
ceramic resonator connected between
internal oscillator.

Internal oscillator is only supported on ADSP-2147x processor
models.
Clocking
The WDT provides three options for the clock source.
1. External clock source can be provided on
2. Ceramic resonator connected between
combined with internal circuitry will generate clock. The ceramic
resonator to be used is either CERALOCK CSTCR4M00G53-R0
(4 MHz) or CERALOCK CSTCC2M00G56-R0 (2 MHz).
3. An internal RC oscillator to provide the clock input. This internal
RC oscillator provides a 2 MHz (typical frequency) clock.
Functional Description
The watchdog timer is used to supervise the stability of the system soft-
ware. Software initializes the 32-bit count value of the timer, and then
enables the timer. Thereafter, the software must reload the counter before
19-4
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pin is continually asserted until the next time
WDTRSTO
For more information, see "Clocking" on page 19-4.
ADSP-214xx SHARC Processor Hardware Reference
and
WDT_CLKIN WDT_CLKO
WDT_CLKIN
and
WDT_CLKIN
or a
WDT_CLKIN
) or from
pin.
pin
WDT_CLKO