Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 207

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For SIMD accesses, if optimization is enabled and the modifier is

set to 2 (even if the modifier is changed, it remains at 2). The

throughput is at maximum if optimization is enabled for sequential

accesses. But in the case of non sequential accesses, throughput is

affected by enabling optimization.

DDR2 Read Optimization

The predictive address given to the memory depends on the

bit values. For example, if the DAG modifier = 2, the

should also be 2, in which case the address + 2 is the predictive value pro-

vided to the DDR2 address pins. Programs may choose to determine

whether read optimization is used or not. If read optimization is disabled,

then each read takes 7 cycles for a CAS latency of 3, even for sequential

With read optimization enabled, 32 sequential reads, with offsets ranging

from 0 to 15, take only 40

be enabled while reading at the external bank boundaries. For example, if

= 1, then 32 locations in the boundary of the external banks

should not be used. These locations can be used without optimization

boundaries of the external bank (if it is fully populated).

By default, the read optimization is enabled (

modifier of 1 (

the DDR2 pointer has a constant modifier. For non-sequential

accesses, turning off optimization provides better results.

Core Accesses

Any break of sequential reads of full page accesses can cause a throughput

loss due to a maximum of eight extra reads.

achieve maximum throughput using core accesses. Any cycle between con-

secutive reads to an DDR2 address results in non-sequential reads.

ADSP-214xx SHARC Processor Hardware Reference

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cycles. Read optimization should not

= 2, then 64 locations cannot be used at the

= 1). Read optimization assumes that

External Port

shows how to

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