Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 803

to 384 words. Since one 32-bit word is created from four packed 8-bit
words, the total number of 8-bit words transmitted is 1536.
Link Port Booting
Booting is supported through link port 0. The
selecting link port boot is 100.
The booting procedure is the same as any other boot mode. The acknowl-
edge signal (
LACK0
a receiver. The host initiates the transfer by toggling the link port clock
( ). Boot data is shifted in 8-bits every clock cycle through the
LCLK0
pins. The received data streams of 4 x 8-bit is packed by the 2 deep
buffer into 32-bit words, least significant bit (LSB) first, and passed into
the internal memory
port 0 interrupt (P1I) occurs. If
P1I is programmed as link port 0 interrupt at reset and the interrupt is
unmasked at reset. Otherwise, P1I is programmed as an
reset.

For link port boot,
deasserted.
LDATA[7:0]
Figure 23-9. Link Port Data Packing
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
) is asserted at
RESET
(Figure 23-9). Once the DMA is completed, a link
BOOT_CFG2–0
should only be asserted after
LCK0
32
32
DMA
System Design
BOOT_CFG2–0
since the link port is configured as
is 100 (link port 0 boot),
SPIHI
Internal
Memory
values for
LDAT0x
RXLP0
interrupt at
has
RESETOUT
23-21