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FFT Accelerator
DMA Channels and TCB Structure
The accelerator has two DMA channels that connect to internal memory.
The channels fetch the data and coefficients from internal memory and
store the results to internal memory. The DMA controller supports circu-
lar buffer chain pointer DMA. Separate TCBs must be created for both
input and output DMA.
Note that bit 20 of the input chain pointer register (
whether the TCB is for loading data or coefficients. If the TCB is a coeffi-
cient TCB, then circular buffering is not supported and the input length
and base registers are ignored.
Table 2-20 on page 2-18
and output TCB structures.
Chained DMA
The DMA controller supports circular buffer chain pointer DMA. The
input TCB structure consists of index, modify, count and chain-pointer
register values for input data. The input TCB also consists of length and
base pointer register values to support circular buffering. Similar to the
input TCB structure, the output TCB also consists of index, modify,
count, chain pointer, length and base pointer register values to support
circular buffered chained DMA for output data.
Once the accelerator is enabled, it loads the TCB values pointed to by the
chain pointer register value into its internal registers. The FFT accelerator
uses the input TCB values to fetch coefficients and data. It then computes
the FFT on the fetched data without any core intervention. Once the
computing is complete, the results are stored into the internal memory of
the processor using the TCB values of the output TCB registers. If the
repeat bit (
FFT_RPT
frame once the current FFT frame is processed.
6-16
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and
Table 2-21 on page 2-18
) is set, the accelerator goes continues on a new FFT
ADSP-214xx SHARC Processor Hardware Reference
) indicates
FFTICP
show the input
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