Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 276

Functional Description
ORIGINAL MASTER
DMA TRANSFER COMPLETE
LTRQ INTERRUPT ENABLED
LACK ASSERTION CAUSES LTRQ INTERRUPT
LINK PORT Tx NON DMA ENABLED
SEND TRW 4 TIMES TO FILL LINK PORT
FIFOS ON BOTH SIDES
CHECK LCTL FOR SLAVE READ OF TRW
BEFORE ACCEPTANCE TEST
CHECK LCTL TO SEE IF SLAVE ACCEPTED
TOKEN BY EMPTYING FIFOS IN
ALLOTTED TIME PERIOD
SET UP LINK PORT FOR CORE Rx TO
ACCEPT DMA SIZE
SET UP LINK PORT FOR Rx DMA AND
DMA COMPLETE IRQ
DMA TRANSFER COMPLETE
SET UP LINK PORT FOR CORE Rx
Figure 4-8. Token Passing Flow Chart
4-12
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ADSP-214xx SHARC Processor Hardware Reference
ORIGINAL SLAVE
DMA TRANSFER COMPLETE
LINK PORT CORE Rx ENABLED
READ RECEIVE BUFFER
TEST FOR TRW
ACCEPT TOKEN BY EMPTYINGLINK PORT
FIFOS THROUGH 3 MORE READS WITHIN
THE ALLOTTED TIME PERIOD
DISABLE LINK PORT AND LTRQ INTERRUPT
POLL LSRQ STATUS FOR LINK PORT
TRANSMIT REQUEST TO ENSURE THAT
THE ORIGINAL MASTER IS NOW A SLAVE
LACK ASSERTION ASSURES THAT IT IS
SAFE TO BEGIN TRANSMITTING
SET UP LINK PORT FOR CORE Tx TO
SEND DMA SIZE
SET UP LINK PORT FOR Tx DMA AND
DMA COMPLETE INTERRUPT
DMA TRANSFER COMPLETE
SET UP LBUF FOR CORE Tx