Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 731

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For DMA, the transmit interrupt is generated when a DMA in transmit

mode is complete whereas the receive interrupt is generated when a receive

DMA is complete or when a receive error occurs. The

reports whether the interrupt is due to DMA completion or errors.

For information on using the UART for DMA transfers, see

Transfers" on page

Peripheral Interrupt

Core Interrupts

The UART has two interrupt outputs referred to as the UART RX and

UART TX interrupts. This is somewhat misleading in that in core mode

all interrupts are grouped together as a single interrupt (

Even though the UART has two interrupts for receive and trans-

mit, in core mode, all interrupts are grouped as a single receive

The UART interrupt enable register (

for core system handling of empty or full states of UART data registers.

Unless polling is used as a means of action, the

bits in this register are normally set.

Setting the bits of this register in core mode enables the UART to inter-

rupt the processor for each word of data. For proper operation in this

mode, system interrupts must be enabled, and appropriate interrupt han-

dling routines must be present. For backward compatibility, the

request is cleared by writing new data to the

transfers, the UART module immediately issues an interrupt.

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

"Interrupts" on page

bit is set in the

UART Port Controller

) is used to enable requests

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