Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 590

Interrupts
Receiver Interrupts
The following three receiver status bits (
interrupt.
• No audio (
• Emphasized audio (
• Status change (
Note the Status change interrupt is generated if any of the 40 status bits
(bytes 4–0) have changed.
Receiver Error Interrupts
The following five receiver error status bits (
interrupt.
• Receiver Locked (
• Validity (
• No Audio Stream (
• CRC Error (
• Parity or biphase Error (
Notice that parity error and biphase error are ORed together to form a
DIR_ERROR_INT
register. The
CRCCERROR
check of the channel status bits fails. The CRCC check is only performed
if channel status bit 0 of byte 0 is high, indicating professional mode.
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DIR_NOAUDIO_INT
DIR_EMPHASIS_INT
DIR_STATCNG_INT
DIR_LOCK_INT
)
DIR_VALID_INT
DIR_NOSTREAM_INT
DIR_CRCERROR_INT
DIR_ERROR_INT
interrupt. The
CRCCERROR
interrupt latch bit is set whenever the CRCC
ADSP-214xx SHARC Processor Hardware Reference
) generate an
DAI_IRPTL_x
)
)
)
DAI_IRPTL_x
)
)
)
)
bit is not available in
) generate an
DIRSTAT