Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 763

• Set the
grammed first).
• Set the
receive. This should be done before the addressing phase of
the next transfer begins.
•
TWIMCOMP
This interrupt is generated because all data has been transferred
( = 0). If no errors were generated, a start condition is initi-
DCNT
ated. At this time, program the following bits of
register:
• Clear
• Re-program
receive.
•
TWISERR
This interrupt is generated due to the arrival of a byte into the
receive FIFO. Simple data handling is all that is required.
Receive/Transmit Repeated Start Sequence
Figure 21-12 illustrates a repeated start data receive followed by a data
transmit sequence. The shading indicates the slave has the bus.
S 7-BIT ADDRESS ACK
XMTSERV INTERRUPT
Figure 21-12. Receive/Transmit Data Repeated Start
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bit (or earlier when
RSTART
bit to indicate the next transfer direction is
TWIMDIR
interrupt
(if this is the last transfer).
RSTART
with the desired number of bytes to
DCNT
interrupt
8-BIT DATA ACK
MCOMP INTERRUPT
Two Wire Interface Controller
TWIMCTL
S 7-BIT ADDRESS ACK
register is pro-
TWI_MASTER_CTRL
8-BIT DATA ACK P
RCVSERV INTERRUPT
MCOMP INTERRUPT
21-25