Chain Pointer Registers - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Table 2-9. Data Buffers (Cont'd)
Buffer Name
UARTRBR0
UARTTHR0
Accelerator input
Accelerator output
MTM read/write
DFEP0–1
AMIRX
AMITX
TXTWI8
TXTWI16
RXTWI8
RXTWI16
MLB local buffer
Some data buffers provide debug support to enable the buffer hang disable
( ) bit. This feature can be enabled in the dedicated peripheral control
BHD
register for the IDP, SPORT, link port, UART0 and the TWI.

Chain Pointer Registers

The chain pointer registers, described in
(SPORTs) and
bits are the memory address field. Like other I/O processor address regis-
ters, the chain pointer register's value is offset to match the starting
address of the processor's internal memory before it is used by the I/O
processor. On the SHARC processor, this offset value is 0x80000.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
FIFO Depth
1
1
8
8
2
6
1
1
1 (1 byte)
1 (2 bytes)
1 (1 byte)
1 (2 bytes)
124
Table 2-12 (external port) are 20 bits wide. The lower 19
I/O Processor
Description
UART0 Receiver
UART0 Transmitter
FFT DMA only
FFT DMA only
DMA only
DMA only
AMI Receive Packer
AMI Transmit Packer
TWI Transmit
TWI Transmit
TWI Receive
TWI Receivet
MLB SRAM
Table 2-10 (generic), Table 2-11
2-11