Operation In Master Mode - Analog Devices AD9739 Manual

AD9739

Operation in Master Mode

Setting Register 0x10, Bit 5 high sets the controller to master
mode. This enables the sync logic to enter an initialization
phase that adjusts the SYNC_OUT_x delay. By moving the
SYNC_OUT_x delay, the SYNC_IN_x sampling point is moved
and the edge transitions of Phase 0 and Phase 1 clocks can be
determined. After the edges are found, the SYNC_OUT_x delay
line is adjusted such that the SYNC_IN_x sampling point is
now placed in the center, away from the edge transitions, as
shown in Figure 93.
The sync controller also attempts to automatically select a phase
for the SYNC_OUT_x signal that is closest to the DCI. This
operation is performed to eliminate the arbitrary phase
relationship of the clock divider upon power-up. After the
SYNC_OUT_x delay is set and the phase is determined, the
master performs a clock divider phase rotation and enters
tracking mode.
WHERE:
T[N] = (EDGE1[N] + EDGE2[N]) >> 1
S[N] = SYNC_IN[N]
CONTROLLER
CLK PHASE1
SYNC_IN_x
CLK PHASE0
SYNC TRACK DELAY
CLK
S[N]
STEP SIZE
T[N]
TARGET
DIFFERENCE ERROR
S[N]
DIFF
X[N]
ACTUAL
Figure 94. Synchronization Controller Track Mode Computation Block Diagram
Rev. A | Page 44 of 56
PHASE 0
SYNC_IN_x
PHASE 1
Figure 93. Optimal Placement of SYNC_IN_X
In tracking mode, the master cycles the sync track delay line
and stores the delay values for the first phase edge, the SYNC_IN_x
edge, and the second phase edge. These signals are only stored
internally and are not accessible via the SPI. Ideally, the
SYNC_IN_x position is exactly between two phases. The con-
troller automatically adjusts the SYNC_OUT_x delay to keep
the SYNC_IN_x edge centered. This operation is continuously
performed in the background, and the SYNC_OUT_x delay line
is adjusted to maintain proper positioning. The controller loop
is shown in Figure 94.
GOT EDGE2
GOT SYNC
GOT EDGE1
FF
FF
FF
DELAY
SYNC TRACK
DELAY
± K
STEP SIZE
= 1
= 1
= 1
Y[N]
COMPUTED
RESULT