Buffer Status; Core Transfers - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Table of Contents

Buffer Status

The entire receive and transmit path form a 3-stage FIFO. Two

writes/reads can occur to the transmit/receive buffer by the core or DMA

before it signals a full/empty condition. Full/empty status for the link buf-

fer is shown by the

configured as a transmitter, then the FFST bits in the

reflect the status of the

receiver, then the FFST bits in

In applications where the latency of link port DMA transfers to and from

internal memory is too long, or where a process is continuous and has no

block boundaries, the processor core may read or write link buffers

directly using the full or empty status bit of the link buffer to automati-

cally pace the operation. The full or empty status of a particular link

buffer can be determined by reading the

DMA should be disabled if reading or writing to the link port

If a read is attempted from an empty receive buffer, the core stalls (hangs)

until the link port completes reception of a word. If a write is attempted

to a full transmit buffer, the core stalls until the external device accepts the

complete word. Up to four words (2 in the receiver and 2 in the transmit-

ter) may be sent without a stall before the receiver core or DMA must read

a link buffer register.

To support debugging buffer transfers, the processor has a buffer hang dis-

) bit. When set (=1), this bit prevents the processor core from

detecting a buffer-related stall condition, permitting debugging of this

type of stall condition.

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

Link Ports—ADSP-2146x

Table of Contents