Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 913

Table A-51. FIRDEBUGCTL Register Bit Descriptions (RW)
Bits Name
0 FIR_DBGMODE
1 FIR_HLD
2 (WO) FIR_RUN
3 Reserved
4 FIR_DBGMEM
5 FIR_ADRINC
31–6 Reserved
IIR Accelerator Registers
The following sections describe the registers used to program and debug
the FIR accelerator.
IIR Global Control Register (IIRCTL1)
The register, shown in
IIRCTL1
is used to configure the global parameters for the accelerator. These
include number of channels, channel auto iterate, DMA enable, and accel-
erator enable.
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Debug Mode Enable.
0 = Disable
1 = Enable
For local memory access, the FIRCTL1 register can be cleared.
Hold Or Single Step. The function of this bit is based on the
FIR_DBGMEM bit setting.
For FIR_DBGMEM = 0:
1 = Single step
for FIR_DBGMEM = 1:
1 = Hold data
Release MAC. This bit is self clearing after one FIR clock cycle.
Local Memory Access. If set, the data and coefficients memory
can be indirectly accessed.
Address Auto Increment. If this bit is set, the address register
auto increments on DBGMEMWRDAT write and DBG-
MEMRDDAT reads.
Figure A-40 and described in
Registers Reference
Table A-52,
A-87