Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 641

Table 15-7. SPI Interrupt Overview
Interrupt Source Interrupt Condition
SPI (SPI Mode – DMA RX/TX done
3–0, 2 channels) – Core RX buffer full
– Core TX buffer empty
– DMA multi master error
– DMA under/overflow error
The (transfer initiation and interrupt) register determines whether
TIMOD
the interrupt is based on the

If configured to generate an interrupt when
00), the interrupt becomes active 1
set.
During DMA driven transfers, an SPI interrupt is triggered:
1. At the completion of a single DMA transfer when count = 0 and
= 0, or when the last data is transferred externally and
INTETC
= 1.
INTETC
2. At the completion of a number of DMA sequences (if DMA chain-
ing is enabled).
3. When a DMA error has occurred.
Note that the
SPIDMAC
interrupts.
Each of these five interrupts are serviced using the interrupt associated
with the module being used. The primary SPI uses the
and the secondary SPI uses the
rupt occurs (regardless of the cause), the
latched. To service the primary SPI port, unmask (set = 1) the
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Serial Peripheral Interface Ports
Interrupt Completion
Internal transfer completion
for core mode of operation.
For DMA modes,
Internal transfer completion
when INTETC = 0.
External transfer completion
when INTETC = 1.
or
TXSPI RXSPI
register must be initialized properly to enable DMA
interrupt. Whenever an SPI inter-
SPILI
SPILI
Interrupt
Acknowledge
RTI instruction
buffer status.
is full (
SPIRX
cycle after the
PCLK
interrupt
SPIHI
or interrupts are
SPIHI
Default
IVT
P1I,
P18I
=
TIMOD
bit is
RXS
bit
SPIHI
15-25