Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 556

Register Overview
Table 12-3. SRC DAI/SRU Signal Routing
ADSP-214xx Internal Node
Inputs
SRC3–0_CLK_IP_I
SRC3–0_CLK_OP_I
SRC3–0_FS_IP_I
SRC3–0_FS_OP_I
SRC3–0_DAT_IP_I
SRC3–0_TDM_OP_I
Outputs
SRC3–0_DAT_OP_O
SRC3–0_TDM_IP_O
For information on using the SRU, see
page 9-20.
Register Overview
The SRC uses five registers to configure and operate the SRC module. For
complete register and bit descriptions, see
ters" on page A-184.
Control Registers (SRCCTLx). The
the sample rate converters. They also specify the input and output data
format.
Mute Register (SRCMUTE). The
tion of the mute in and mute out signal.
Ratio Registers (SRCRATx). The
ratio between the input and out data stream and mute information (mute
out).
12-4
www.BDTIC.com/ADI
DAI Connection
Group A
Group C
Group B
Group B, D
Group B
"Rules for SRU Connections" on
SRCCTLx
SRCMUTE
SRCRATx
ADSP-214xx SHARC Processor Hardware Reference
SRU Register
SRU_CLK2–1
SRU_FS2–1
SRU_DAT3–2
"Sample Rate Converter Regis-
registers enable or disable
register controls the connec-
registers return the sample