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15 SERIAL PERIPHERAL
INTERFACE PORTS
The ADSP-214xx processors are equipped with two synchronous serial
peripheral interface ports that are compatible with the industry-standard
serial peripheral interface (SPI). Each SPI port also has its own set of regis-
ters (the secondary register set contains a B as in
support communication with a variety of peripheral devices including
codecs, data converters, sample rate converters, S/PDIF or AES/EBU digi-
tal audio transmitters and receivers, LCDs, shift registers,
microcontrollers, and FPGA devices with SPI emulation capabilities. The
interface specifications are shown in
Table 15-1. SPI Port Specifications
Feature
Connectivity
Multiplexed Pinout
SRU DAI Required
SRU DAI Default Routing
SRU2 DPI Required
SRU2 DPI Default Routing
Interrupt Control
Protocol
Master Capable
Slave Capable
Transmission Simplex
Transmission Half Duplex
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
SPIBAUDB
Table
15-1.
SPI/SPIB
No
No
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
). The SPI ports
15-1
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