Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 184

DDR2 DRAM Controller (ADSP-2146x)
different internal banks. For 8 banked devices, the controller does follow
the t specification.
FAW
Precharge
This command is executed by the controller if the address to be accessed
falls in a different page in the same external bank and the same internal
bank. A precharge is not done if the address to be accessed falls in an open
page in another internal or external bank.
For page miss reads or writes, only the external and internal banks to be
accessed by the read or write is pre-charged. For auto-refresh and
self-refresh, all external DDR2 banks are pre-charged at one time.
Precharge All
This command is given to precharge all internal banks. Just before an auto
refresh or self refresh, or during the power up sequence, the controller
always issues the precharge command to all internal DDR2 banks. For
eight bank devices, the t
precharge all command.
Burst Read
The burst read command is initiated by having
while holding
DDR2_RAS
The address inputs determine the starting column address for the burst.
The delay from the start of the command to when the data from the first
cell appears on the outputs is equal to the value of the read latency (RL).
The data strobe output (
valid data (
DDR2_DATA
bit of the burst is synchronized with the rising edge of the data strobe
( ).
DDR2_DQS
Each subsequent data-out appears on the
burst is synchronized with the rising edge of the data strobe (
3-54
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period must be satisfied while performing the
FAW
and high at the rising edge of the clock.
DDR2_WE
) is driven low one clock cycle before
DDR2_DQS
) is driven onto the data bus
ADSP-214xx SHARC Processor Hardware Reference
and
DDR2_CS DDR2_CAS
(Figure 3-12). The first
The first bit of the
DDR2_DATA
low
).
DDR2_DQS