Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 346

FIR Accelerator
1. Program the number of channels in the
FIR_NCH
2. Configure the TCBs in internal memory with one channel's TCB
pointing to the next channel's TCB.
3. Write the first TCB value into the
accelerator.
The accelerator fetches the first channel's TCB and, using it as
pointer, pre-fills the delay line and coefficient memory and loads
the
FIRCTL2
ing to that channel.
The accelerator then calculates output samples corresponding to
one Window and stores the data back in internal memory.
At the end of the Window the accelerator updates the
registers in the TCB of internal memory and moves to the
OIFIR
next channel.
When all the channels are finished and the auto channel iterate
( , bit 9) is set, the accelerator processes the first channel again
CAI
and iterates through the channels. If the
accelerator waits for core intervention.
6-50
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bits (5–1).
register to configure the filter parameters correspond-
ADSP-214xx SHARC Processor Hardware Reference
register using the
FIRCTL1
register and enable the
CPFIR
bit is cleared, the
CAI
and
IIFIR