Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 845

FRZSP (21–19)
Arbitration Freezing
Length for SPORT DMA
FRZCR (14–12)
Arbitration Freezing Length for
CORE Accesses
FRZDMA (10–8)
Arbitration Freezing Length for DMA
DMAPR (7–6)
DMA Channel Priority for CH0 and CH1
EPBR (5–4)
External Port Bus Priority
Figure A-6. EPCTL Register
Table A-8. EPCTL Register Bit Descriptions (RW)
Bit Name
0 B0SD
1 B1SD
2 B2SD
3 B3SD
ADSP-214xx SHARC Processor Hardware Reference
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31 30 29 28 27 26 25 24
15 14 13 12 11 10 9 8
Description
Select Bank 0 DDR2/SDRAM.
0 = Bank 0 non-DDR2
1 = Bank 0 DDR2
Select Bank 1 DDR2.
0 = Bank 1 Non-DDR2
1 = Bank 1 DDR2
Select Bank 2 DDR2 DRAM.
0 = Bank 2 Non-DDR2
1 = Bank 2 DDR2
Select Bank 3 DDR2 DRAM.
0= Bank 3 Non-DDR2
1= Bank 3 DDR2
Registers Reference
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
B0SD
Bank 0 DDR2 DRAM
B1SD
Bank 1 DDR2 DRAM
B2SD
Bank 2 DDR2 DRAM
B3SD
Bank 3 DDR2 DRAM
A-19