Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 535

Table 11-8. IDP_FIFO Register Bit Descriptions
Bit Name
2–0 CHAN_ENC
3 LR_STAT
31–4 SDATA
Core Transfers
The core transfers require that the serial peripheral at the SIP writes data
to the
IDP_DATAx_I
selected input format used. These data are automatically moved to the
register without DMA intervention.
IDP_FIFO
The output of the FIFO can be directly fetched by reading from the
buffer. The
IDP_FIFO
top sample from the FIFO, which is a maximum of eight locations deep.
When this register is read, the corresponding element is removed from the
IDP FIFO, and the next element is moved into the
mechanism is provided to generate an interrupt when more than a speci-
fied number of words are in the FIFO. This interrupt signals the core to
read the
IDP_FIFO
The number of data samples in the FIFO at any time is reflected in the
bit field (bits 31-28 in the
IDP_FIFOSZ
the number of samples in FIFO.
ADSP-214xx SHARC Processor Hardware Reference
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Description
IDP Channel Encoding. These bits indicate the serial input port
channel number that provided this serial input data.
Note: This information is not valid when data comes from the PDAP.
Left/Right Channel Status. Indicates whether the data in bits 31-4 is
the left or the right audio channel as dictated by the frame sync sig-
nal. The polarity of the encoding depends on the serial mode selected
in IDP_SMODE for that channel. See
Input Data (Serial). Some LSBs can be zero, depending on the
mode.
pin ( or DAI pins for PDAP) according to the
DATA
buffer is used only to read and remove the
IDP_FIFO
register.
Input Data Port
Table A-90 on page
IDP_FIFO
register), which tracks
DAI_STAT0
A-176.
register. A
11-15